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tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use pm5363 tupp+622 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces datasheet released issue 4: july 2000
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use revision history issue no. issue date details of change issue 4 july 2000 update for revision b device. de-document tu3 inband error feature. added changes to timing and operating conditions. all input hold times for sclk (19.44mhz) are changed from 1ns to 1.5ns. all output max prop delays for hsclk (77.76mhz) changed from 8ns to 9ns. all output min prop delay for sclk (19.44mhz) changed from 2ns to 3.5ns. operating condition for v dd3.3 changed from 3.3v 10% to 3.3v 0.3v and operating condition for v dd2.5 changed from 2.5v 10% to 2.5v 0.2v. tugen bit and tugbyp bit description changed. device id revision number, sos bit description and boundary scan id changed. issue 3 nov 1999 update data-sheet portion to preliminary. issue 2 may 1999 update pin and register description. issue 1 december 1998 document created.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use i contents 1 features ............................................................................................1 2 applications .....................................................................................5 3 references.......................................................................................6 4 definitions ........................................................................................8 5 application examples ...................................................................9 5.1 sts-12 (stm-4) aggregate interface..............................9 5.2 quad sts-3 (stm-1) aggregate interface ..................10 5.3 sts-48 (stm-16) aggregate interface.......................... 11 5.4 tupp-plus compatibility and tupp+622 feature enhancements...................................................12 6 description.....................................................................................13 7 pin diagram .....................................................................................15 8 block diagram ...............................................................................16 9 pin description (304) ....................................................................17 10 functional description.............................................................88 10.1 input bus demultiplexer ................................................89 10.2 output bus multiplexer..................................................90 10.3 tributary payload processor (vtpp).........................91 10.3.1 clock generator....................................................91 10.3.2 incoming timing generator.................................91
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use ii 10.3.3 incoming multiframe detector.........................92 10.3.4 pointer interpreter .............................................92 10.3.5 payload buffer........................................................96 10.3.6 outgoing timing generator ...............................96 10.3.7 pointer generator ................................................97 10.4 tributary path overhead processor (rtop) ....................................................................................100 10.4.1 clock generator..................................................101 10.4.2 timing generator .................................................101 10.4.3 error monitor.......................................................101 10.4.4 in-band error report .........................................103 10.4.5 extract.....................................................................104 10.5 tributary trace buffer (rttb) ...................................104 10.5.1 clock generator..................................................104 10.5.2 timing generator .................................................105 10.5.3 extract.....................................................................105 10.5.4 alarm monitor .......................................................105 10.5.5 buffer .......................................................................106 10.6 jtag test access port ...................................................106 10.7 microprocessor interface ........................................107 11 normal mode register description ................................... 117 11.1 top level configuration registers......................... 118
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use iii 11.2 vtpp #1, vtpp #2 and vtpp #3 registers ....................169 11.3 rtop #1, rtop #2 and rtop #3 registers ...................205 11.4 rttb #1, rttb #2 and rttb #3 registers.....................298 12 test features description.....................................................325 12.1 i/o test mode......................................................................332 12.2 jtag test port ..................................................................364 13 operation ......................................................................................376 13.1 configuration options .................................................376 13.2 sts-1 mode ..........................................................................378 13.3 au3 mode..............................................................................378 13.4 au4 mode..............................................................................379 13.5 bypass options .................................................................381 13.6 power sequencing..........................................................382 13.7 jtag support .....................................................................382 13.7.1 tap controller .....................................................384 13.7.2 boundary scan instructions...........................387 14 functional timing.......................................................................389 15 absolute maximum ratings .....................................................408 16 d.c. characteristics .................................................................409 17 microprocessor interface timing characteristics .........................................................................412 18 tupp+622 timing characteristics .........................................420
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use iv 19 ordering and thermal information....................................431 20 mechanical information ..........................................................434
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use v list of registers register 00h: stp incoming configuration ................................. 118 register 01h: stp outgoing configuration................................120 register 02h: stp input signal activity monitor #1, accumulation trigger .............................................................122 register 03h: stp reset and identity.............................................124 register 04h: stp vtpp #1 configuration #1 ................................125 register 05h: stp vtpp #2 configuration #1 ................................128 register 06h: stp vtpp #3 configuration #1 ................................131 register 07h: stp tributary payload processor and lom interrupt enable...............................................................134 register 08h: stp tributary payload processor interrupt and lom status .......................................................136 register 09h: stp parity error and lom interrupt .................138 register 0ah: stp rtop and rttb interrupt enable.................140 register 0bh: stp rtop and rttb interrupt status .................142 register 0ch: stp rtop #1 and rttb #1 configuration ............144 register 0dh: stp rtop #2 and rttb #2 configuration ............146 register 0eh: stp rtop #3 and rttb #3 configuration.............148 register 10h: stp tributary alarm ais control ........................150 register 11h: stp tributary remote defect indication control ....................................................................152
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use vi register 12h: stp tributary auxiliary remote defect indication control ....................................................................154 register 13h: stp tributary path defect indication control .........................................................................................157 register 14h: stp input signal activity monitor #2..................159 register 15h: stp outgoing pointer lsb ......................................161 register 17h: stp vtpp #1 configuration #2 ................................163 register 18h: stp vtpp #2 configuration #2 ................................165 register 19h: stp vtpp #3 configuration #2 ................................167 register 20h, 40h, 60h: vtpp, tu3 or tu #1 in tug2 #1, configuration and status ......................................................169 register 21h-26h, 41h-46h, 61h-66h: vtpp, tu #1 in tug2 #2 to tug2 #7, configuration and status ...........................172 register 27h, 47h, 67h: vtpp, tu3 or tu #1 in tug2 #1 to tug2 #7, lop interrupt ..............................................................174 register 28h-2eh, 48h-4eh, 68h-6eh: vtpp, tu #2 in tug2 #1 to tug2 #7, configuration and status ...........................176 register 2fh, 4fh, 6fh: vtpp, tu #2 in tug2 #1 to tug2 #7, lop interrupt ........................................................................178 register 30h-36h, 50h-56h, 70h-76h: vtpp, tu #3 in tug2 #1 to tug2 #7, configuration and status ...........................179 register 37h, 57h, 77h: vtpp, tu #3 in tug2 #1 to tug2 #7, lop interrupt ........................................................................181 register 38h-3eh, 58h-5eh, 78h-7eh: vtpp, tu #4 in tug2 #1 to tug2 #7, configuration and status ...........................182 register 3fh, 5fh, 7fh: vtpp, tu #4 in tug2 #1 to tug2 #7, lop interrupt ........................................................................184
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use vii register a0h, c0h, e0h: vtpp, tu3 or tu #1 in tug2 #1, alarm status ................................................................................185 register a1h-a6h, c1h-c6h, e1h-e6h: vtpp, tu #1 in tug2 #2 to tug2 #7, alarm status .....................................................188 register a7h, c7h, e7h: vtpp, tu3 or tu #1 in tug2 #1 to tug2 #7, ais interrupt ...............................................................191 register a8h-aeh, c8h-ceh, e8h-eeh: vtpp, tu #2 in tug2 #1 to tug2 #7, alarm status .....................................................193 register afh, cfh, efh: vtpp, tu #2 in tug2 #1 to tug2 #7 ais interrupt ...........................................................................196 register b0h-b6h, d0h-d6h, f0h-f6h: vtpp, tu #3 in tug2 #1 to tug2 #7, alarm status .....................................................197 register b7h, d7h, f7h: vtpp, tu #3 in tug2 #1 to tug2 #7, ais interrupt ..........................................................................200 register b8h-beh, d8h-deh, f8h-feh: vtpp, tu #4 in tug2 #1 to tug2 #7, alarm status .....................................................201 register bfh, dfh, ffh: vtpp, tu #4 in tug2 #1 to tug2 #7, ais interrupt ..........................................................................204 register 100h, 200h, 300h: rtop, tu3 or tu #1 in tug2 #1, configuration .............................................................................205 register 101h, 201h, 301h: rtop, tu3 or tu #1 in tug2 #1, configuration and alarm status .........................................208 register 102h, 202h, 302h: rtop, tu3 or tu #1 in tug2 #1, expected path signal label.................................................... 211 register 103h, 203h, 303h: rtop, tu3 or tu #1 in tug2 #1, accepted path signal label ...................................................212 register 104h, 204h, 304h: rtop, tu3 or tu #1 in tug2 #1, bip-2/bip-8 error count lsb.....................................................213
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use viii register 105h, 205h, 305h: rtop, tu3 or tu #1 in tug2 #1, bip-2/bip-8 error count msb....................................................213 register 106h, 206h, 306h: rtop, tu3 or tu #1 in tug2 #1, rei error count lsb..................................................................215 register 107h, 207h, 307h: rtop, tu3 or tu #1 in tug2 #1, rei error count msb.................................................................215 register 108h, 110h, 118h, 120h, 128h, 130h: register 208h, 210h, 218h, 220h, 228h, 230h: register 308h, 310h, 318h, 320h, 328h, 330h: rtop, tu #1 in tug2 #2 to tug2 #7, configuration .......................................................217 register 109h, 111h, 119h, 121h, 129h, 131h: register 209h, 211h, 219h, 221h, 229h, 231h: register 309h, 311h, 319h, 321h, 329h, 331h: rtop, tu #1 in tug2 #2 to tug2 #7, configuration and alarm status ...................220 register 10ah, 112h, 11ah, 122h, 12ah, 132h: register 20ah, 212h, 21ah, 222h, 22ah, 232h: register 30ah, 312h, 31ah, 322h, 32ah, 332h: rtop, tu #1 in tug2 #2 to tug2 #7, expected path signal label .............................223 register 10bh, 113h, 11bh, 123h, 12bh, 133h: register 20bh, 213h, 21bh, 223h, 22bh, 233h: register 30bh, 313h, 31bh, 323h, 32bh, 333h: rtop, tu #1 in tug2 #2 to tug2 #7, accepted path signal label .............................224 register 10ch, 114h, 11ch, 124h, 12ch, 134h: register 20ch, 214h, 21ch, 224h, 22ch, 234h: register 30ch, 314h, 31ch, 324h, 32ch, 334h: rtop, tu #1 in tug2 #2 to tug2 #7, bip-2 error count lsb ........................................225 register 10dh, 115h, 11dh, 125h, 12dh, 135h: register 20dh, 215h, 21dh, 225h, 22dh, 235h: register 30dh, 315h, 31dh, 325h, 32dh, 335h: rtop, tu #1 in tug2 #2 to tug2 #7, bip-2 error count msb .......................................225 register 10eh, 116h, 11eh, 126h, 12eh, 136h: register 20eh, 216h, 21eh, 226h, 22eh, 236h: register 30eh,
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use ix 316h, 31eh, 326h, 32eh, 336h: tu #1 in tug2 #2 to tug2 #7, rei error count lsb .................................................227 register 10fh, 117h, 11fh, 127h, 12fh, 137h: register 20fh, 217h, 21fh, 227h, 22fh, 237h: register 30fh, 317h, 31fh, 327h, 32fh, 337h: tu #1 in tug2 #2 to tug2 #7, rei error count msb ................................................227 register 138h, 238h, 338h: rtop, tu3 or tu #1 in tug2 #1 to tug2 #7, copsl interrupt ...................................................229 register 139h, 239h, 339h: rtop, tu3 or tu #1 in tug2 #1 to tug2 #7, pslm interrupt .....................................................231 register 13ah, 23ah, 33ah: rtop, tu3 or tu #1 in tug2 #1 to tug2 #7, pslu interrupt......................................................233 register 13bh, 23bh, 33bh: rtop, tu3 or tu #1 in tug2 #1 to tug2 #7, rdi interrupt .........................................................235 register 13ch, 23ch, 33ch: rtop, tu3 auxiliary rdi interrupt or tu #1 in tug2 #1 to tug2 #7 rfi interrupt ......................................................................................237 register 13dh, 23dh, 33dh: rtop, tu #1 in tug2 #1 to tug2 #7, in band error reporting configuration .............................................................................239 register 13eh, 23eh, 33eh: rtop, tu3 or tu #1 in tug2 #1 to tug2 #7, controllable output configuration .............................................................................240 register 140h, 148h, 150h, 158h, 160h, 168h, 170h: register 240h, 248h, 250h, 258h, 260h, 268h, 270h: register 340h, 348h, 350h, 358h, 360h, 368h, 370h: rtop, tu #2 in tug2 #1 to tug2 #7, configuration .............241 register 141h, 149h, 151h, 159h, 161h, 169h, 171h: register 241h, 249h, 251h, 259h, 261h, 269h, 271h: register 341h, 349h, 351h, 359h, 361h, 369h, 371h:
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use x rtop, tu #2 in tug2 #1 to tug2 #7, configuration and alarm status........................................................................244 register 142h, 14ah, 152h, 15ah, 162h, 16ah, 172h: register 242h, 24ah, 252h, 25ah, 262h, 26ah, 272h: register 342h, 34ah, 352h, 35ah, 362h, 36ah, 372h: rtop, tu #2 in tug2 #1 to tug2 #7, expected path signal label..................................................................................247 register 143h, 14bh, 153h, 15bh, 163h, 16bh, 173h: register 243h, 24bh, 253h, 25bh, 263h, 26bh, 273h: register 343h, 34bh, 353h, 35bh, 363h, 36bh, 373h: rtop, tu #2 in tug2 #1 to tug2 #7, accepted path signal label..................................................................................248 register 144h, 14ch, 154h, 15ch, 164h, 16ch, 174h: register 244h, 24ch, 254h, 25ch, 264h, 26ch, 274h: register 344h, 34ch, 354h, 35ch, 364h, 36ch, 374h: rtop, tu #2 in tug2 #1 to tug2 #7, bip-2 error count lsb.......................................................................................249 register 145h, 14dh, 155h, 15dh, 165h, 16dh, 175h: register 245h, 24dh, 255h, 25dh, 265h, 26dh, 275h: register 345h, 34dh, 355h, 35dh, 365h, 36dh, 375h: rtop, tu #2 in tug2 #1 to tug2 #7, bip-2 error count msb......................................................................................249 register 146h, 14eh, 156h, 15eh, 166h, 16eh, 176h: register 246h, 24eh, 256h, 25eh, 266h, 26eh, 276h: register 346h, 34eh, 356h, 35eh, 366h, 36eh, 376h: rtop, tu #2 in tug2 #1 to tug2 #7, rei error count lsb.......................................................................................251 register 147h, 14fh, 157h, 15fh, 167h, 16fh, 177h: register 247h, 24fh, 257h, 25fh, 267h, 26fh, 277h: register 347h, 34fh, 357h, 35fh, 367h, 36fh, 377h: rtop, tu #2 in tug2 #1 to tug2 #7, rei error count msb......................................................................................251 register 178h, 278h, 378h: rtop, tu #2 in tug2 #1 to tug2 #7, copsl interrupt .........................................................253
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xi register 179h, 279h, 379h: rtop, tu #2 in tug2 #1 to tug2 #7, pslm interrupt ...........................................................254 register 17ah, 27ah, 37ah: rtop, tu #2 in tug2 #1 to tug2 #7, pslu interrupt............................................................255 register 17bh, 27bh, 37bh: rtop, tu #2 in tug2 #1 to tug2 #7, rdi interrupt...............................................................256 register 17ch, 27ch, 37ch: rtop, tu #2 in tug2 #1 to tug2 #7, rfi interrupt ...............................................................257 register 17dh, 27dh, 37dh: rtop, tu #2 in tug2 #1 to tug2 #7, in band error reporting configuration .............................................................................258 register 17eh, 27eh, 37eh: tu #2 in tug2 #1 to tug2 #7, controllable output configuration ................................259 register 180h, 188h, 190h, 198h, 1a0h, 1a8h, 1b0h: register 280h, 288h, 290h, 298h, 2a0h, 2a8h, 2b0h: register 380h, 388h, 390h, 398h, 3a0h, 3a8h, 3b0h: rtop, tu #3 in tug2 #1 to tug2 #7, configuration .............260 register 181h, 189h, 191h, 199h, 1a1h, 1a9h, 1b1h: register 281h, 289h, 291h, 299h, 2a1h, 2a9h, 2b1h: register 381h, 389h, 391h, 399h, 3a1h, 3a9h, 3b1h: rtop, tu #3 in tug2 #1 to tug2 #7, configuration and alarm status........................................................................263 register 182h, 18ah, 192h, 19ah, 1a2h, 1aah, 1b2h: register 282h, 28ah, 292h, 29ah, 2a2h, 2aah, 2b2h: register 382h, 38ah, 392h, 39ah, 3a2h, 3aah, 3b2h: rtop, tu #3 in tug2 #1 to tug2 #7, expected path signal label..................................................................................266 register 183h, 18bh, 193h, 19bh, 1a3h, 1abh, 1b3h: register 283h, 28bh, 293h, 29bh, 2a3h, 2abh, 2b3h: register 383h, 38bh, 393h, 39bh, 3a3h, 3abh, 3b3h: rtop, tu #3 in tug2 #1 to tug2 #7, accepted path signal label..................................................................................267
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xii register 184h, 18ch, 194h, 19ch, 1a4h, 1ach, 1b4h: register 284h, 28ch, 294h, 29ch, 2a4h, 2ach, 2b4h: register 384h, 38ch, 394h, 39ch, 3a4h, 3ach, 3b4h: rtop, tu #3 in tug2 #1 to tug2 #7, bip-2 error count lsb.......................................................................................268 register 185h, 18dh, 195h, 19dh, 1a5h, 1adh, 1b5h: register 285h, 28dh, 295h, 29dh, 2a5h, 2adh, 2b5h: register 385h, 38dh, 395h, 39dh, 3a5h, 3adh, 3b5h: rtop, tu #3 in tug2 #1 to tug2 #7, bip-2 error count msb......................................................................................268 register 186h, 18eh, 196h, 19eh, 1a6h, 1aeh, 1b6h: register 286h, 28eh, 296h, 29eh, 2a6h, 2aeh, 2b6h: register 386h, 38eh, 396h, 39eh, 3a6h, 3aeh, 3b6h: tu #3 in tug2 #1 to tug2 #7, rei error count lsb.............270 register 187h, 18fh, 197h, 19fh, 1a7h, 1afh, 1b7h: register 287h, 28fh, 297h, 29fh, 2a7h, 2afh, 2b7h: register 387h, 38fh, 397h, 39fh, 3a7h, 3afh, 3b7h: rtop, tu #3 in tug2 #1 to tug2 #7, rei error count msb......................................................................................270 register 1b8h, 2b8h, 3b8h: rtop, tu #3 in tug2 #1 to tug2 #7, copsl interrupt .........................................................272 register 1b9h, 2b9h, 3b9h: rtop, tu #3 in tug2 #1 to tug2 #7, pslm interrupt ...........................................................273 register 1bah, 2bah, 3bah: rtop, tu #3 in tug2 #1 to tug2 #7, pslu interrupt............................................................274 register 1bbh, 2bbh, 3bbh: rtop, tu #3 in tug2 #1 to tug2 #7, rdi interrupt...............................................................275 register 1bch, 2bch, 3bch: rtop, tu #3 in tug2 #1 to tug2 #7, rfi interrupt ...............................................................276 register 1bdh, 2bdh, 3bdh: rtop, tu #3 in tug2 #1 to tug2 #7, in band error reporting configuration .............................................................................277
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xiii register 1beh, 2beh, 3beh: rtop, tu #3 in tug2 #1 to tug2 #7, controllable output configuration................278 register 1c0h, 1c8h, 1d0h, 1d8h, 1e0h, 1e8h, 1f0h: register 2c0h, 2c8h, 2d0h, 2d8h, 2e0h, 2e8h, 2f0h: register 3c0h, 3c8h, 3d0h, 3d8h, 3e0h, 3e8h, 3f0h: rtop, tu #4 in tug2 #1 to tug2 #7, configuration .............279 register 1c1h, 1c9h, 1d1h, 1d9h, 1e1h, 1e9h, 1f1h: register 2c1h, 2c9h, 2d1h, 2d9h, 2e1h, 2e9h, 2f1h: register 3c1h, 3c9h, 3d1h, 3d9h, 3e1h, 3e9h, 3f1h: rtop, tu #4 in tug2 #1 to tug2 #7, configuration and alarm status........................................................................281 register 1c2h, 1cah, 1d2h, 1dah, 1e2h, 1eah, 1f2h: register 2c2h, 2cah, 2d2h, 2dah, 2e2h, 2eah, 2f2h: register 3c2h, 3cah, 3d2h, 3dah, 3e2h, 3eah, 3f2h: rtop, tu #4 in tug2 #1 to tug2 #7, expected path signal label..................................................................................284 register 1c3h, 1cbh, 1d3h, 1dbh, 1e3h, 1ebh, 1f3h: register 2c3h, 2cbh, 2d3h, 2dbh, 2e3h, 2ebh, 2f3h: register 3c3h, 3cbh, 3d3h, 3dbh, 3e3h, 3ebh, 3f3h: rtop, tu #4 in tug2 #1 to tug2 #7, path signal label................................................................................................285 register 1c4h, 1cch, 1d4h, 1dch, 1e4h, 1ech, 1f4h: register 2c4h, 2cch, 2d4h, 2dch, 2e4h, 2ech, 2f4h: register 3c4h, 3cch, 3d4h, 3dch, 3e4h, 3ech, 3f4h: rtop, tu #4 in tug2 #1 to tug2 #7, bip-2 error count lsb.........................................................................286 register 1c5h, 1cdh, 1d5h, 1ddh, 1e5h, 1edh, 1f5h: register 2c5h, 2cdh, 2d5h, 2ddh, 2e5h, 2edh, 2f5h: register 3c5h, 3cdh, 3d5h, 3ddh, 3e5h, 3edh, 3f5h: rtop, tu #4 in tug2 #1 to tug2 #7, bip-2 error count msb........................................................................286 register 1c6h, 1ceh, 1d6h, 1deh, 1e6h, 1eeh, 1f6h: register 2c6h, 2ceh, 2d6h, 2deh, 2e6h, 2eeh, 2f6h: register 3c6h, 3ceh, 3d6h, 3deh, 3e6h, 3eeh, 3f6h:
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xiv rtop, tu #4 in tug2 #1 to tug2 #7, rei error count lsb.......................................................................................288 register 1c7h, 1cfh, 1d7h, 1dfh, 1e7h, 1efh, 1f7h: register 2c7h, 2cfh, 2d7h, 2dfh, 2e7h, 2efh, 2f7h: register 3c7h, 3cfh, 3d7h, 3dfh, 3e7h, 3efh, 3f7h: rtop, tu #4 in tug2 #1 to tug2 #7, rei error count msb......................................................................................288 register 1f8h, 2f8h, 3f8h: rtop, tu #4 in tug2 #1 to tug2 #7, copsl interrupt .........................................................290 register 1f9h, 2f9h, 3f9h: rtop, tu #4 in tug2 #1 to tug2 #7, pslm interrupt ...........................................................291 register 1fah, 2fah, 3fah: rtop, tu #4 in tug2 #1 to tug2 #7, pslu interrupt............................................................292 register 1fbh, 2fbh, 3fbh: rtop, tu #4 in tug2 #1 to tug2 #7, rdi interrupt...............................................................293 register 1fch, 2fch, 3fch: rtop, tu #4 in tug2 #1 to tug2 #7, rfi interrupt ...............................................................294 register 1fdh, 2fdh, 3fdh: rtop, tu #4 in tug2 #1 to tug2 #7, in band error reporting configuration .............................................................................295 register 1feh, 2feh, 3feh: rtop, tu #4 in tug2 #1 to tug2 #7, controllable output configuration................296 register 1ffh, 2ffh, 3ffh: rtop status .........................................297 register 400h, 440h, 480h: rttb, tu3 or tu #1 in tug2 #1, configuration and status ......................................................298 register 401h-406h, 441h-446h, 481h-486h: rttb, tu #1 in tug2 #2 to tug2 #7, configuration and status.................300 register 408h-40eh, 448h-44eh, 488h-48eh: rttb, tu #2 in tug2 #1 to tug2 #7, configuration and status.................302
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xv register 410h-416h, 450h-456h, 490h-496h: rttb, tu #3 in tug2 #1 to tug2 #7, configuration and status.................304 register 418h-41eh, 458h-45eh, 498h-49eh: rttb, tu #4 in tug2 #1 to tug2 #7, configuration and status.................306 register 420h, 460h, 4a0h: rttb, tu3 or tu #1 in tug2 #1 to tug2 #7, tim interrupt .........................................................308 register 421h, 461h, 4a1h: rttb, tu #2 in tug2 #1 to tug2 #7, tim interrupt ...............................................................310 register 422h, 462h, 4a2h: rttb, tu #3 in tug2 #1 to tug2 #7, tim interrupt ............................................................... 311 register 423h, 463h, 4a3h: rttb, tu #4 in tug2 #1 to tug2 #7, tim interrupt ...............................................................312 register 424h, 464h, 4a4h: rttb, tu3 or tu #1 in tug2 #1 to tug2 #7, tiu interrupt .........................................................313 register 425h, 465h, 4a5h: rttb, tu #2 in tug2 #1 to tug2 #7, tiu interrupt ...............................................................315 register 426h, 466h, 4a6h: rttb, tu #3 in tug2 #1 to tug2 #7, tiu interrupt ...............................................................316 register 427h, 467h, 4a7h: rttb, tu #4 in tug2 #1 to tug2 #7, tiu interrupt ...............................................................317 register 428h, 468h, 4a8h: rttb, tiu threshold...........................318 register 429h, 469h, 4a9h: rttb, indirect tributary select .............................................................................................320 register 42ah, 46ah, 4aah: rttb, indirect address select .............................................................................................322 register 42bh, 46bh, 4abh: rttb, indirect data select ............324 register 2000h: master test .............................................................329
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xvi register 2001h: stp select ................................................................331 test register 2002h: (write in i/o test mode) ..............................333 test register 2003h: (write in i/o test mode) ..............................334 test register 2004h: (write in i/o test mode) ..............................335 test register 2005h: (write in i/o test mode) ..............................336 test register 2006h: (write in i/o test mode) ..............................337 test register 2802h: (write in i/o test mode) ..............................338 test register 2803h: (write in i/o test mode) ..............................339 test register 2804h: (write in i/o test mode) ..............................340 test register 2805h: (write in i/o test mode) ..............................341 test register 2806h: (write in i/o test mode) ..............................342 test register 3002h: (write in i/o test mode) ..............................343 test register 3003h: (write in i/o test mode) ..............................344 test register 3004h: (write in i/o test mode) ..............................345 test register 3005h: (write in i/o test mode) ..............................346 test register 3006h: (write in i/o test mode) ..............................347 test register 3802h: (write in i/o test mode) ..............................348 test register 3803h: (write in i/o test mode) ..............................349 test register 3804h: (write in i/o test mode) ..............................350 test register 3805h: (write in i/o test mode) ..............................351 test register 3806h: (write in i/o test mode) ..............................352
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xvii test register 2002h: (read in i/o test mode) ...............................353 test register 2003h: (read in i/o test mode) ...............................354 test register 2004h: (read in i/o test mode) ...............................355 test register 2802h: (read in i/o test mode) ...............................356 test register 2803h: (read in i/o test mode) ...............................357 test register 2804h: (read in i/o test mode) ...............................358 test register 3002h: (read in i/o test mode) ...............................359 test register 3003h: (read in i/o test mode) ...............................360 test register 3004h: (read in i/o test mode) ...............................361 test register 3802h: (read in i/o test mode) ...............................362 test register 3803h: (read in i/o test mode) ...............................363 test register 3804h: (read in i/o test mode) ...............................364
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xviii list of figures figure 1 - sts-12 (stm-4) aggregate interface with tributary processing and performance monitoring................9 figure 2 - quad sts-3 (stm-1) aggregate interface with tributary processing and performance monitoring ................................................................................................10 figure 3 - sts-48 (stm-16) aggregate interface with tributary processing and performance monitoring.............. 11 figure 4 - stm-4 (sts-12) order of byte transmission ..............89 figure 5 - pointer interpretation state diagram......................93 figure 6 - pointer generation state diagram.............................98 figure 7 - input observation cell (input, clock input) ..........374 figure 8 - output cell (output, clock output, output enable).......................................................................................374 figure 9 - bidirectional cell (io_cell)..........................................375 figure 10- i/o cell (i/o with oe pair).................................................375 figure 11 - sonet sts-3 carrying vt1.5 within sts-1 ..................378 figure 12- sdh stm-1 carrying tu12 within vc3/au3 ..................379 figure 13- sdh stm-1 carrying tu12 within tug3/au4 ................379 figure 14- sdh stm-1 carrying tu3 within tug3..........................380 figure 15- sdh stm-1 carrying mix of tu11, tu12, tu3 within tug3/au4.......................................................................................381 figure 16- boundary scan architecture.....................................383 figure 17- tap controller finite state machine .......................385
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xix figure 18- stm-1 input bus timing - simple sts-1/au3 case 390 figure 19- stm-1 input bus timing - complex sts-1 / au3 case 391 figure 20- stm-1 input bus timing - sts-1 / au3 (vt/tu pointer interpretation disabled) ..................................................392 figure 21- stm-1 input bus timing - au4 case ................................393 figure 22- stm-4 input bus timing - sts-1/au3 case.....................394 figure 23- stm-1 output bus timing - sts-1 spes / au3 vcs case 396 figure 24- stm-1 output bus timing - au4 vc case ......................398 figure 25- stm-4 output bus timing - sts-1 spes / au3 vcs case 399 figure 26- stm-1 (sts-3) interface, by-passed and normal transport frame delay functional timing.................400 figure 27- stm-4 (sts-12) interface, by-passed and normal transport frame delay functional timing.................401 figure 28- tributary path overhead serialization functional timing..................................................................................404 figure 29- receive alarm port functional timing....................407 figure 30- microprocessor interface read access timing (intel mode) ................................................................................413 figure 31- microprocessor interface read access timing (motorola mode)......................................................................414 figure 32- microprocessor interface write access timing (intel mode) ................................................................................417
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xx figure 33- microprocessor interface write access timing (motorola mode)......................................................................418 figure 34- input timing.........................................................................422 figure 35- stream output timing .....................................................425 figure 36- path overhead output timing......................................427 figure 37- jtag port interface timing...........................................429 figure 38- theta ja vs. airflow plot ..............................................432 figure 39- mechanical drawing 304 pin super ball grid array (sbga)...................................................................................434
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use xxi list of tables table 1 - path signal label mismatch state ..............................102 table 2 - register memory map.....................................................107 table 3 - test mode register memory map ...............................325 table 4 - instruction register (length ? 3 bits) ....................364 table 5 -identification register ..................................................365 table 6 boundary scan register (length ? 218 bits)............365 table 7 -tupp+622 absolute maximum ratings .............................408 table 8 -tupp+622 d.c. characteristics .........................................409 table 9 - microprocessor interface read access...............412 table 10 - microprocessor interface write access .............416 table 11 - tupp+622 input timing for sclk (figure 34) .............420 table 12 - tupp+622 input timing hsclk (figure 34) ...................421 table 13 - tupp+622 stream output................................................424 table 14 - tupp+622 path overhead output (figure 36)...........426 table 15 - jtag port interface (figure 37) ..................................428 table 16 - ordering information....................................................431 table 17 - thermal information ? theta jc..................................431 table 18 - maximum junction temperature.................................431 table 19 - thermal information ? theta ja vs. airflow 432
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 1 1 features ? configurable, multi-channel, payload processor for aligning sonet virtual tributaries (vts) (sdh tributary units, tus) in an sts-12 or four sts-3 (an stm-4 or four stm-1) byte serial data streams. ? four tupp+622 may be used in parallel to support sts-48 (stm-16) applications. ? transfers all incoming tributaries in the twelve sts-1 synchronous payload envelopes of an sts-12 or four sts-3 byte serial streams to the corresponding twelve sts-1 synchronous payload envelopes of an outgoing sts-12 or four outgoing sts-3 byte serial streams. ? transfers all incoming tributaries in the four au4 or twelve au3 administrative units of an stm-4 or four stm-1 byte serial streams to the corresponding four au4 or twelve au3 administrative units of an outgoing stm-4 or four outgoing stm-1 byte serial streams. ? compensates for pleisiochronous relationships between incoming and outgoing higher level (sts-1, au4, au3) payload frame rates through processing of the lower level (vt6, vt3, vt2, vt1.5, tu3, tu2, tu12, or tu11) tributary pointers. ? provides software configurable offset between the payload frame boundaries and the transport frame boundary on a per sts-3 or stm-1 basis. ? optionally bypasses the tributary pointer interpretation function. tributary payload frame boundaries and payload bytes are identified by signals coincident with the incoming data stream. ? configurable to process any legal mix of vt1.5, vt2, vt3, vt6, tu11, tu12, tu2, or tu3 tributaries. each vt group or tug2 can be configured to carry one of four tributary types. tug2s can be multiplexed into vc3s or tug3s. each tug3 can also be configured to carry a single tu3. ? independently configurable for au3 or au4 frame format on incoming and outgoing interfaces.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 2 ? configurable to process 16-byte or 64-byte format tributary path trace messages (tributary trail trace identifiers). ? optionally frames to the h4 byte in the path overhead to determine tributary multiframe boundaries. inserts internally generated h4 bytes with leading logic 1 bits into the outgoing administrative units. ? extracts and serializes the entire tributary path overhead of each tributary into lower speed serial streams. ? extracts tributary size (ss) bits of each tributary into internal registers. ? detects loss of pointer (lop) and re-acquisition for each tributary and optionally generates interrupts. ? detects tributary path alarm indication signal (ais) and return to normal state for each tributary and optionally generates interrupts. ? detects tributary elastic store underflow and overflow errors and optionally generates interrupts. ? extracts tributary path trace message (trail trace identifier) of each tributary into internal buffers. ? provides individual tributary path trace message buffer that holds the expected message and detects tributary path trace mismatch (trail trace identifier mismatch) alarms (tim) and return to matched state for each tributary and optionally generates interrupts. ? detects tributary path trace unstable (trail trace identifier unstable) alarms (tiu) and return to stable state for each tributary and optionally generates interrupts. ? extracts tributary path signal label for each tributary into internal registers and detects change of tributary path signal label events (copsl) of each tributary and optionally generates interrupts. ? provides individual tributary path signal label register that hold the expected label and detects tributary path signal label mismatch alarms (pslm) and return to matched state for each tributary and optionally generates interrupts.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 3 ? detects tributary path signal label unstable alarms (pslu) and return to stable state for each tributary and optionally generates interrupts. ? detects tributary unequipped defect (uneq) and tributary path defect indication (pdi-v). ? detects assertion and removal of tributary extended remote defect indications (rdi) for each tributary and optionally generates interrupts. ? calculates and compares the tributary path bip-2 error detection code for each tributary and configurable to accumulate the bip-2 errors, on block or bit basis, in internal registers. ? calculates and compares the tu3 path bip-8 error detection code for each tu3 stream and accumulates the bip-8 errors, on block or bit basis, in internal registers. ? accumulates tu3 tributary remote error indications (rei) on a bit or a block basis, in internal registers. ? allows insertion of all-zeros or all-ones tributary idle code with unequipped indication and valid pointer into any tributary under software control. idle tributaries are identified by an output signal. ? identifies outgoing tributaries that are in ais state by an output signal. allows software to force the ais insertion on a per tributary basis. ? inserts valid h4 byte and all-zeros fixed stuff bytes on the outgoing stream. remaining path overhead bytes (j1, b3, c2, g1, f2, z3, z4, and z5) can be configured to be set to all-zeros or to reflect the value of the corresponding poh bytes in the incoming stream. ? inserts valid pointers (h1, h2), framing bytes (a1, a2), and all-zeros transport overhead bytes on the outgoing stream with valid "telecombus" control signals. ? supports in-band error reporting by updating the rei, rdi and auxiliary rdi bits in the v5 byte (g1 in tu3) with the status of the incoming stream.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 4 ? provides low maximum tributary processing delay of 33 s for vt1.5, 25 s for vt2, 17 s for vt3, and 9 s for vt6 streams. ? verifies parity on the ic1j1 and ipl signals and on the incoming data stream and generates parity on the outgoing data stream. ? may be used for multiframe synchronization or ring closure at the head-end node of a sonet/sdh ring. ? operates in conjunction with the pm5313 spectra-622 sonet/sdh payload extractor/aligner for 622 mbit/s or the pm5342 spectra-155 sonet/sdh payload extractor/aligner to align tributaries such that they can be switched by the pm5371 tudx sonet/sdh tributary unit cross- connect. provides backwards compatibility with the pm5362 tupp sonet/sdh tributary unit payload processor / performance monitor. ? independently configurable incoming and outgoing interfaces that operate in the19.44 mhz stm-1 (sts-3) or the 77.76 mhz stm-4 (sts-12) byte interface modes. ? provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. ? provides a standard 5 signal ieee p1149.1 jtag test port for boundary scan test purposes. ? low power, +2.5 volt, cmos technology, +3.3 volt ttl compatible inputs and outputs (5v tolerant). ? 304 pin super bga package.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 5 2 applications ? sonet/sdh digital cross-connect ? sonet/sdh add-drop multiplexer
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 6 3 references 1. american national standard for telecommunications ? synchronous optical network (sonet) ? basic description including multiplex structures, rates, and formats, ansi t1.105-1995. 2. committee t1 contribution, "draft of t1.105 - sonet rates and formats", t1x1.5/94-033r2-1994. 3. committee t1 contribution, "payload defect indication (pdi): triggers, switch priorities, timing and proposed text", t1x1.5/94-135r1, 1994. 4. committee t1 contribution, "proposed itu-t contribution on enhanced path rdi for sdh", t1x1.5/94-117, 1994. 5. itu, recommendation g.708 - "network node interface for the synchronous digital hierarchy", 1993. 6. itu, recommendation g.709 - "synchronous multiplexing structure", 1993. 7. itu, recommendation g.782 - "types and general characteristics of synchronous digital hierarchy (sdh) equipment", january 1994. 8. itu, recommendation g.783 - "characteristics of synchronous digital hierarchy (sdh) equipment functional blocks", april 1997. 9. bell communications research - sonet transport systems: common generic criteria, tr-tsy-000253, issue 2, december 1991. 10. bell communications research - sonet transport systems: common generic criteria, gr-253-core, issue 2, rev. 1, december 1997. 11. bell communications research - sonet add-drop multiplex equipment (sonet adm) generic criteria, gr-496, issue 1, december 1998. 12. bell communications research - sonet dual-fed unidirectional path switched ring (upsr) equipment generic criteria, gr-1400-core, issue 2, january 1999.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 7 13. european telecommunications standards institute, transmission and multiplexing (tm); generic functional requirements for sdh transmission equipment, part 1, generic process and performance, ets 300 417-1-1, january 1996. 14. pmc-981215 ?pm669 (0.25um ram test chip) and p25 (galax! i/o test chip) rev. a characterization report?. issue 1. february 9, 1999. 15. pmc-1991211 ?PM5363-BI rev. a (tupp+622) characterization report?. issue 1. march 27, 2000.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 8 4 definitions the following table defines the abbreviations for the tupp+622. vtpp tributary payload processor rtop tributary overhead processor rttb tributary trace buffer stp stm-1 (sts-3) tributary processor
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 9 5 application examples the tupp+622 can be used in sonet/sdh network elements including switches, terminal multiplexers, and add-drop multiplexers. in such applications, the tupp+622 performs vt (tu) pointer processing to align the virtual tributaries to facilitate cross-connecting and sonet ring closure. the tupp+622 also performs performance monitoring of any legal mix of tributaries to implement intermediate performance monitoring. the tupp+622 is well suited to process data from one sts-12 (stm-4), four sts-3?s (stm-1?s) or one quarter of an sts-48 (stm-16). 5.1 sts-12 (stm-4) aggregate interface figure 1 shows how the tupp+622 is used to implement a single 77.76 mhz sts-12 (stm-4) aggregate interface. in this application, the pm5313 spectra- 622 performs sonet/sdh section, line and path termination and the pm5363 tupp+622 performs tributary pointer processing and performance monitoring. figure 1 - sts-12 (stm-4) aggregate interface with tributary processing and performance monitoring optical transceiver pm5313 spectra-622 rxd+/- sd txd+/- ac1j1v1[1] apl[1] dpl[1] ack ad[7:0], adp[1] dd[7:0], ddp[1] dc1j1v1[1] dck 77.76 mhz 8-bit high speed telecombus interface drop add 622 mbit/s optical interface pm5363 tupp+622 opl[1] od[7:0], odp[1] oc1j1v1[1] ipl[1] ic1j1[1] hsclk id[7:0], idp[1]
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 10 5.2 quad sts-3 (stm-1) aggregate interface the system side interface of the tupp+622 can be configured to interface to four spectra-155's telecombus interface. figure 2 shows how the tupp+622 is connected to quad sts-3 (stm-1) aggregate interface using four 19.44 mhz telecom buses on the system side interface. in this application, the pm5342 spectra-155's perform sonet/sdh section, line and path termination and the pm5363 tupp+622 performs tributary pointer processing and performance monitoring. figure 2 - quad sts-3 (stm-1) aggregate interface with tributary processing and performance monitoring optical transceiver pm5342 spectra-155 rxd+/- sd txd+/- ac1j1v1 apl dpl ack ad[7:0], adp dd[7:0], ddp dc1j1v1 dck 155 mbit/s optical interface ipl[4] ic1j1[4] id[31:23], idp[4] four 19.44 mhz 8-bit high speed telecombus interface pm5363 tupp+622 opl[4] od[31:24], odp[4] oc1j1v1[4] sclk optical transceiver pm5342 spectra-155 rxd+/- sd txd+/- ac1j1v1 apl dpl ack ad[7:0], adp dd[7:0], ddp dc1j1v1 dck 155 mbit/s optical interface ipl[4] ic1j1[4] id[31:24], idp[4] optical transceiver pm5342 spectra-155 rxd+/- sd txd+/- ac1j1v1 apl dpl ack ad[7:0], adp dd[7:0], ddp dc1j1v1 dck 155 mbit/s optical interface ipl[3] ic1j1[3] id[23:16], idp[3] optical transceiver pm5342 spectra-155 rxd+/- sd txd+/- ac1j1v1 apl dpl ack ad[7:0], adp dd[7:0], ddp dc1j1v1 dck 155 mbit/s optical interface ipl[2] ic1j1[2] id[15:8], idp[2] opl[3] od[23:16], odp[3] oc1j1v1[3] opl[2] od[15:8], odp[2] oc1j1v1[2] opl[1] od[7:0], odp[1] oc1j1v1[1] sclk ipl[1] ic1j1[1] id[7:0], idp[1]
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 11 5.3 sts-48 (stm-16) aggregate interface four pm5363 tupp+622 devices can be connected to four pm5313 spectra- 622 devices and an oc-48 front end transceiver device to implement an sts-48 (stm-16) aggregate interface. figure 3 shows a block diagram for the sts-48 (stm-16) application. in this application, the oc-48 transceiver performs sonet/sdh section and line processing, the spectra-622 devices perform sonet/sdh path processing, line rate decoupling, and pointer processing, and the tupp+622 devices perform vt (tu) pointer processing and performance monitoring. figure 3 - sts-48 (stm-16) aggregate interface with tributary processing and performance monitoring oc-48 serial to parallel and parallel to serial conversion oc-48 front end pout[7:0] pin[7:0] 2488 mbit/s optical interface oc-48 clock recovery pm5313 spectra-622 ac1j1v1[1] apl[1] dpl[1] ack ad[7:0], adp[1] dd[7:0], ddp[1] dc1j1v1[1] dck pm5363 tupp+622 opl[1] od[7:0], odp[1] oc1j1v1[1] gsclk_fp ipl[1] ic1j1[1] hsclk id[7:0], idp[1] tout[7:0] td[7:0] pin[7:0] fpin rout[7:0] rofp tfpo tfpi pm5313 spectra-622 ac1j1v1[1] apl[1] dpl[1] ack ad[7:0], adp[1] dd[7:0], ddp[1] dc1j1v1[1] dck pm5363 tupp+622 opl[1] od[7:0], odp[1] oc1j1v1[1] gsclk_fp ipl[1] ic1j1[1] hsclk id[7:0], idp[1] tout[7:0] td[7:0] pin[7:0] fpin rout[7:0] rofp tfpo tfpi pm5313 spectra-622 ac1j1v1[1] apl[1] dpl[1] ack ad[7:0], adp[1] dd[7:0], ddp[1] dc1j1v1[1] dck pm5363 tupp+622 opl[1] od[7:0], odp[1] oc1j1v1[1] gsclk_fp ipl[1] ic1j1[1] hsclk id[7:0], idp[1] tout[7:0] td[7:0] pin[7:0] fpin rout[7:0] rofp tfpo tfpi pm5313 spectra-622 ac1j1v1[1] apl[1] dpl[1] ack ad[7:0], adp[1] dd[7:0], ddp[1] dc1j1v1[1] dck pm5363 tupp+622 opl[1] od[7:0], odp[1] oc1j1v1[1] gsclk_fp ipl[1] ic1j1[1] hsclk id[7:0], idp[1] tout[7:0] td[7:0] pin[7:0] fpin rout[7:0] rofp tfpo tfpi
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 12 5.4 tupp-plus compatibility and tupp+622 feature enhancements the tupp+622 (pm5363) supports software configuration of the payload frame alignment in the outgoing data stream. the high order path active offset may be set to any alignment on a per-stm-1 (sts-3) basis. for example, by setting the outgoing stream active offset contained in the stp outgoing pointer msb and lsb registers in stm-1 (sts-3) tributary processor #1 (stp #1) to zero, the j1 byte(s) of the outgoing au3/au4 in stm-1 (sts-3) #1 will be aligned to the first payload byte(s) immediately following the h3 bytes. similarly, the j1 byte(s) can be aligned to the payload byte(s) immediately after the j0/z0 bytes of the section overhead by setting the outgoing stream active offset to 522. in the tupp-plus (pm5362), arbitrary placement of payload frame boundaries, is supported by placing the device in floating mode and supplying the device with an outgoing payload active signal (opl) and a payload frame alignment signal (j1 portion of oc1j1). since the tupp+622 supports this feature in software, floating mode is no longer required. consequently, the oc1j1 and opl signals are deleted. the transport frame alignment of the outgoing data stream corresponds to a delayed version of the incoming data stream. to improve signal naming consistency in the tupp+622, the tupp-plus equivalent lc1j1v1 and lpl signals are renamed to oc1j1v1 and opl, respectively. an input generated system clock frame position (gsclk_fp) signal is added to the tupp+622 to enable externally alignment of the gsclk generation and related internal operation of the device when the 77.76 mhz stm-4 interface mode is selected for the incoming or outgoing interface. this feature allows a deterministic transport frame delay through the tupp+622 to be set. this is essential when multiple tupp+622 devices have to be aligned in processing data streams with aggregate bandwidth greater than an stm-4.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 13 6 description the pm5363 tupp+622 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces is a monolithic integrated circuit that implements a configurable, multi-channel, payload processor that aligns and monitors performance of sonet virtual tributaries (vts) or sdh tributary units (tus.). when configured for sonet compatible operation, the tupp+622 transfers all incoming tributaries in the twelve sts-1 synchronous payload envelopes of an sts-12 or four sts-3 byte serial streams to the corresponding twelve sts-1 synchronous payload envelopes of an outgoing sts-12 or four outgoing sts-3 byte serial streams. similarly, when configured for sdh compatible operation, the tupp+622 transfers all incoming tributaries in the four au4 or twelve au3 administrative units of an stm-4 or four stm-1 byte serial streams to the corresponding four au4 or twelve au3 administrative units of an outgoing stm-4 or four outgoing stm-1 byte serial streams. the tupp+622 compensates for pleisiochronous relationships between incoming and outgoing higher level (sts- 1, au4, au3) synchronous payload envelope frame rates through processing of the lower level (vt6, vt3, vt2, vt1.5, tu3, tu2, tu12, tu11) tributary pointers. the incoming and outgoing data streams are configurable independently. the tupp+622 is configurable to process any legal mix of tributaries. each vt group can be configured to carry any one of the four tributary types (vt1.5, vt2, vt3, or vt6) and each tug2 can be configured to carry any one of three tributary types (tu11, tu12, or tu2). tug2s can be multiplexed into a vc3 or a tug3. alternatively, each tug3 can be configured to carry a tu3. the tupp+622 operates in conjunction with the pm5313 spectra-622 sonet/sdh payload extractor/aligner for 622 mbit/s or the pm5342 spectra-155 sonet/sdh payload extractor/aligner to align tributaries such that they can be switched by the pm5371 tudx sonet/sdh tributary unit cross-connect. the tupp+622 provides useful maintenance functions. they include, for each tributary, detection of loss of pointer, detection of ais alarm, detection of tributary path signal label mismatch and unstable alarms, detection of tributary path trace mismatch and unstable alarms. optionally, interrupts can be generated due to the assertion and removal of any of the above alarm conditions. the tupp+622 counts received tributary path bip-2 (bip-8 for tu3) errors on a block or bit basis
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 14 and counts rei indications. the tupp+622 also allows insertion of tributary path ais as a consequence of any of the above alarm conditions. in addition, the tupp+622 may insert tributary idle (unequipped) into any tributary. incoming tributary path trace messages and path signal labels are stored in a set of microprocessor accessible registers. the tupp+622 can also insert inverted new data flag fields that can be used to diagnose downstream pointer processing elements. no auxiliary high speed clocks are required as the tupp+622 operates from either a single 19.44 mhz or a single 77.76 mhz line rate clock. the tupp+622 is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. the tupp+622 is implemented in low power, +2.5 volt core and +3.3 volt i/o, cmos technology. it has ttl compatible inputs and outputs and is packaged in a 304 pin sbga package.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 15 7 pin diagram the tupp+622 is packaged in a 304 pin sbga package having a body size of 31 mm by 31 mm and a pin pitch of 1.27 mm. 2322212019181716151413121110987654321 a vdd vss poh[4] iais[2] idp[2] vss id[12] vss ic1j1[2] d[7] d[3] vss d[0] a[11] a[8] vss a[3] vss ale csb tdo vss vdd a b vss vdd vss pohfp [4] itpl[2] id[15] vddi13 id[10] id[8] vddi14 d[4] d[1] vddi15 a[10] a[6] a[4] a[1] rdb vddi16 tdi vss vdd vss b c pohfp [6] vss vdd pohfp [5] rad[2] itv5[2] id[14] id[11] id[9] intb d[5] d[2] a[13] a[9] a[5] a[2] wrb mbeb tck tms vdd vss od[0] c d otmf[2] poh[6] poh[5] vdd pohen [4] vdd itmf[2] id[13] vdd ipl[2] d[6] vdd a[12] a[7] vdd a[0] rstb vdd trstb vdd oc1j1v1 [1] od[1] od[3] d e od[8] vddi12 pohen [6] pohen [5] opl[1] od[2] od[4] od[7] e f vss od[9] oc1j1v1 [2] vdd vdd od[5] odp[1] vss f g od[14] od[12] od[10] opl[2] od[6] otv5[1] vddi1 ais[1] g h vss od[15] od[13] od[11] otpl[1] idle[1] tpoh[1] vss h j otpl[2] vddi11 odp[2] vdd vdd cout[1] otmf[1] gsclk_fp j k tpoh[2] idle[2] ais[2] otv5[2] hsclk rad[1] vddi2 pohfp [1] k l opl[3] oc1j1v1 [3] otmf[3] cout[2] pm5363 tupp+622 poh[1] pohen [1] pohck pohfp [2] l m vss od[16] od[17] vdd vdd poh[2] pohen [2] vss m n od[18] vddi10 od[19] od[20] bottom view gsclk [1] gsclk [0] vddi3 pohfp [3] n p od[21] od[22] od[23] otv5[3] ipl[1] pohen [3] poh[3] sclk p r odp[3] otpl[3] ais[3] vdd vdd id[1] id[0] ic1j1[1] r t vss idle[3] tpoh[3] rad[3] id[5] id[4] id[2] vss t u cout[3] vddi9 pohfp [7] pohfp [8] itmf[1] id[6] vddi4 id[3] u v vss poh[7] poh[8] vdd vdd itv5[1] id[7] vss v w pohen [7] pohen [8] poh[9] itpl[3] ipl[4] ihsmodeb itpl[1] idp[1] w y pohfp [9] pohen [9] itv5[3] vdd idp[3] vdd id[17] nc2 vdd otv5[4] od[28] vdd pohen [12] poh[11] vdd iais[4] nc1 vdd id[26] vdd id[24] ohsmodeb iais[1] y aa iais[3] vss vdd itmf[3] id[21] id[18] ic1j1[3] cout[4] ais[4] od[31] od[27] od[24] otmf[4] pohfp [12] pohen [10] pohfp [10] itpl[4] idp[4] id[29] id[25] vdd vss ic1j1[4] aa ab vss vdd vss id[22] id[19] ipl[3] vddi8 idle[4] otpl[4] od[30] vddi7 od[25] oc1j1v1 [4] vddi6 pohfp [11] poh[10] vddi5 itv5[4] id[31] id[28] vss vdd vss ab ac vdd vss id[23] id[20] id[16] vss tpoh[4] vss odp[4] od[29] od[26] vss opl[4] poh[12] pohen [11] vss rad[4] vss itmf[4] id[30] id[27] vss vdd ac 2322212019181716151413121110987654321
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 16 8 block diagram output mux od[31:0] otmf[4:1] gsclk_fp otpl[4:1] otv5[4:1] odp[4:1] ais[4:1] idle[4:1] oc1j1v1[4:1] tpoh[4:1] pohfp[12:1] pohen[12:1] poh[12:1] pohck rad[4:1] cout[4:1] opl[4:1] id [31:0] id p [4:1] sclk ic1j1[4:1] input demux ip l[4:1 ] itmf[4:1] hsclk ihsmodeb ohsmodeb gsclk[1:0] rstb csb rdb wrb ale a[13:0] mbeb d[7:0] microprocessor inte rface in tb jtag controller tck tms tdi trstb tdo tributary payload processor (vtpp) tributary path processor (rtop) overhead tributary trace buffer (r ttb) tributary payload processor (vtpp) tributary path processor (rtop) overhead tributary trace buffer (r ttb) itv5[4:1] itpl[4:1] ia is[4:1] stm-1 (sts-3) tributary processor (stp) #1, #2, #3, #4 tributary payload processor (vtpp) tributary path processor (rtop) overhead tributary trace buffer (rttb)
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 17 9 pin description (304) pin name type pin no. function sclk/ input p1 the system clock (sclk) provides timing for tupp+622 internal operations. sclk is a 19.44 mhz, nominally 50% duty cycle, clock. when either incoming interface is in stm-4 mode (ihsmodeb set low) or the outgoing interface is in stm-4 mode (ohsmodeb set low), sclk must be connected to gsclk[0] externally. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), ic1j1[4:1], ipl[4:1], itmf[4:1], idp[4:1], id[31:0], itv5[4:1], itpl[4:1], iais[4:1] and otmf[4:1] are sampled on the rising edge of sclk. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), odp[4:1], otpl[4:1], otv5[4:1], od[31:0], ais[4:1], idle[4:1], tpoh[4:1], oc1j1v1[4:1] and opl[4:1] are updated on the rising edge of sclk. vclk the test vector clock (vclk) signal is used during tupp+622 production testing to verify manufacture.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 18 pin name type pin no. function hsclk input k4 the high-speed stm-4 (sts-12) interface mode system clock (hsclk) provides timing for tupp+622 internal operations in incoming or outgoing stm-4 (sts-12) interface mode (ihsmodeb or ohsmodeb set low). hsclk is a 77.76 mhz, nominally 50% duty cycle, clock. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), ic1j1[1], ipl[1], itmf[1], idp[1], id[7:0], itv5[1], itpl[1] and iais[1] are sampled on the rising edge of hsclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), otmf[1] and gsclk_fp are sampled on the rising edge of hsclk, and odp[1], otpl[1], otv5[1], od[7:0], ais[1], idle[1], tpoh[1], oc1j1v1[1] and opl[1] are updated on the rising edge of hsclk. when the incoming and the outgoing interfaces are in stm-1 mode (ihsmodeb and ohsmodeb both set high), hsclk may be left unconnected. hsclk has an integral pull-up resistor.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 19 pin name type pin no. function ihsmodeb input w3 the active low incoming high-speed interface mode signal (ihsmodeb) configures the incoming interface mode of the tupp+622. when ihsmodeb is set low, the 77.76 mhz stm-4 (sts-12) interface mode is selected. sclk must be connected to gsclk[0]. ic1j1[1], ipl[1], itmf[1], idp[1], id[7:0], itv5[1], itpl[1], iais[1] are sampled on the rising edge of hsclk. when ihsmodeb is set high, the 19.44 mhz stm-1 (sts-3) interface mode is selected. ic1j1[4:1], ipl[4:1], itmf[4:1], idp[4:1], id[31:0], itv5[4:1], itpl[4:1], iais[4:1] are sampled on the rising edge of sclk. ihsmodeb has an integral pull- up resistor. ohsmodeb input y2 the outgoing high-speed interface mode signal (ohsmodeb) configures the outgoing interface mode of the tupp+622. when ohsmodeb is set low, the 77.76 mhz stm-4 (sts-12) interface mode is selected. sclk must be connected to gsclk[0]. otmf[1] and gsclk_fp are sampled on the rising edge of hsclk. odp[1], otpl[1], otv5[1], od[7:0], ais[1], idle[1], oc1j1v1[1] and opl[1] are updated on the rising edge of hsclk. when ohsmodeb is set high, the 19.44 mhz stm-1 (sts-3) interface mode is selected. otmf[4:1] are sampled on the rising edge of sclk. odp[4:1], otpl[4:1], otv5[4:1], od[31:0], ais[4:1], idle[4:1], oc1j1v1[4:1] and opl[4:1] are updated on the rising edge of sclk. ohsmodeb has an integral pull-up resistor.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 20 pin name type pin no. function gsclk[1] gsclk[0] output n4 n3 the generated system clock (gsclk[1:0]) signals provide timing for the tupp+622 when stm-4 (sts-12) interface mode is selected at the incoming or outgoing interface (ihsmodeb or ohsmodeb set low). gsclk[1:0] are a divide by four of hsclk. gsclk[0] must only be connected to sclk externally when ihsmodeb or ohsmodeb is set low. gsclk[1] is a exact replica of gsclk[0] and can be used to supply timing to external devices that are operating in the 19.44 mhz stm-1 (sts-3) interface timing domain. gsclk[1:0] are updated on the rising edge of hsclk.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 21 pin name type pin no. function ic1j1[1] input r1 the input c1/j1 frame pulse #1 (ic1j1[1]) identifies the transport envelope and synchronous payload envelope frame boundaries on the incoming stm-4 or stm-1 #1 stream (id[7:0]). in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), ic1j1[1] is set high while ipl[1] is low to mark the first c1 byte of the stm-1 #1 transport envelope frame on the id[7:0] bus. the c1 byte position must be coincident to the c1 byte positions of the stm-1 streams on id[15:8], id[23:16] and id[31:24]. ic1j1[1] is set high while ipl[1] is high to mark each j1 byte of the synchronous payload envelope(s) on the id[7:0] bus. ic1j1[1] must be present at every occurrence of the first c1 and all j1 bytes. the tupp+622 will ignore a pulse on ic1j1[1] at the byte position of the v1 byte of the first tributary of each vc3 or the top byte of the first fixed stuff column of each tug3. ic1j1[1] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), ic1j1[1] is set high while ipl[1] is low to mark the first c1 byte of the stm-4 transport envelope frame on the id[7:0] bus. ic1j1[1] is set high while ipl[1] is high to mark each j1 byte of the synchronous payload envelopes on the id[7:0] bus. ic1j1[1] must be present at every occurrence of the first c1 and all j1 bytes. the tupp+622 will ignore a pulse on ic1j1[1] at the byte position of the v1 byte of the first tributary of each vc3 or the top byte of the first fixed stuff column of each tug3. ic1j1[1] is sampled on the rising edge of hsclk.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 22 pin name type pin no. function ic1j1[2] input a15 the input c1/j1 frame pulse #2 (ic1j1[2]) identifies the transport envelope and synchronous payload envelope frame boundaries on the incoming stm-1 #2 stream (id[15:8]). in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), ic1j1[2] is set high while ipl[2] is low to mark the first c1 byte of the stm-1 #2 transport envelope frame on the id[15:8] bus. the c1 byte position must be coincident to the c1 byte positions of the stm-1 streams on id[7:0], id[23:16] and id[31:24]. ic1j1[2] is set high while ipl[2] is high to mark each j1 byte of the synchronous payload envelope(s) on the id[15:8] bus. ic1j1[2] must be present at every occurrence of the first c1 and all j1 bytes. the tupp+622 will ignore a pulse on ic1j1[2] at the byte position of the v1 byte of the first tributary of each vc3 or the top byte of the first fixed stuff column of each tug3. ic1j1[2] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), ic1j1[2] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 23 pin name type pin no. function ic1j1[3] input aa17 the input c1/j1 frame pulse #3 (ic1j1[3]) identifies the transport envelope and synchronous payload envelope frame boundaries on the incoming stm-1 #3 stream (id[23:16]). in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), ic1j1[3] is set high while ipl[3] is low to mark the first c1 byte of the stm-1 #3 transport envelope frame on the id[23:16] bus. the c1 byte position must be coincident to the c1 byte positions of the stm-1 streams on id[7:0], id[15:8] and id[31:24]. ic1j1[3] is set high while ipl[3] is high to mark each j1 byte of the synchronous payload envelope(s) on the id[23:16] bus. ic1j1[3] must be present at every occurrence of the first c1 and all j1 bytes. the tupp+622 will ignore a pulse on ic1j1[3] at the byte position of the v1 byte of the first tributary of each vc3 or the top byte of the first fixed stuff column of each tug3. ic1j1[3] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), ic1j1[3] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 24 pin name type pin no. function ic1j1[4] input aa1 the input c1/j1 frame pulse #4 (ic1j1[4]) identifies the transport envelope and synchronous payload envelope frame boundaries on the incoming stm-1 #4 stream (id[31:24]). in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), ic1j1[4] is set high while ipl[4] is low to mark the first c1 byte of the stm-1 #4 transport envelope frame on the id[31:24] bus. the c1 byte position must be coincident to the c1 byte positions of the stm-1 streams on id[7:0], id[15:8] and id[23:16]. ic1j1[4] is set high while ipl[4] is high to mark each j1 byte of the synchronous payload envelope(s) on the id[31:24] bus. ic1j1[4] must be present at every occurrence of the first c1 and all j1 bytes. the tupp+622 will ignore a pulse on ic1j1[4] at the byte position of the v1 byte of the first tributary of each vc3 or the top byte of the first fixed stuff column of each tug3. ic1j1[4] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), ic1j1[4] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 25 pin name type pin no. function ipl[1] input p4 the active high incoming payload active #1 (ipl[1]) signal identifies the bytes within the transport envelope frame on the incoming stm- 4 or stm-1 #1 stream that carry vc3 or vc4 virtual containers, or sts-1 synchronous payload envelopes. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), ipl[1] must be brought high to mark each payload byte on id[7:0]. ipl[1] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), ipl[1] must be brought high to mark each payload byte on id[7:0]. ipl[1] is sampled on the rising edge of hsclk. ipl[2] input d14 the active high incoming payload active #2 (ipl[2]) signal identifies the bytes within the transport envelope frame on the incoming stm- 1 #2 stream that carry vc3 or vc4 virtual containers, or sts-1 synchronous payload envelopes. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), ipl[2] must be brought high to mark each payload byte on id[15:8]. ipl[2] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), ipl[2] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 26 pin name type pin no. function ipl[3] input ab18 the active high incoming payload active #3 (ipl[3]) signal identifies the bytes within the transport envelope frame on the incoming stm- 1 #3 stream that carry vc3 or vc4 virtual containers, or sts-1 synchronous payload envelopes. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), ipl[3] must be brought high to mark each payload byte on id[23:16]. ipl[3] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), ipl[3] is unused and must be strapped low. ipl[4] input w4 the active high incoming payload active #4 (ipl[4]) signal identifies the bytes within the transport envelope frame on the incoming stm- 1 #4 stream that carry vc3 or vc4 virtual containers, or sts-1 synchronous payload envelopes. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), ipl[4] must be brought high to mark each payload byte on id[31:24]. ipl[4] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), ipl[4] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 27 pin name type pin no. function itmf[1] input u4 the active high incoming tributary multiframe #1 (itmf[1]) signal identifies the first frame of the tributary multiframe for each sts-1 synchronous payload envelope, au3, or au4 administrative unit in the stm-4 or stm-1 #1 stream (id[7:0]). itmf[1] is enabled by setting the corresponding itmfen register bit high. when itmfen bit is low, the path overhead h4 byte is used to determine tributary multiframe boundaries. itmf[1] is selectable to pulse high during the third byte after j1 of the first frame of the tributary multiframe or during the h4 byte which indicates that the next frame is the first frame of the tributary multiframe. selection between marking each h4 or the third byte after each j1 is controlled by the corresponding itmfh4 register bit. pulses on itmf[1] are only effective during the h4 or third byte after each j1 byte positions, as appropriate. when itmfh4 is low, itmf[1] can be set high for the entire first frame of the tributary multiframe. itmf[1] must be low for the 2 nd , 3 rd , and 4 th frame of the tributary multiframe. when itmfh4 is high, itmf[1] can be set high for the entire fourth frame of the tributary multiframe. itmf[1] must be low for the 1 st , 2 nd and 3 rd frame of the tributary multiframe. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), itmf[1] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), itmf[1] is sampled on the rising edge of hsclk.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 28 pin name type pin no. function itmf[2] input d17 the active high incoming tributary multiframe #2 (itmf[2]) signal identifies the first frame of the tributary multiframe for each sts-1 synchronous payload envelope, au3, or au4 administrative unit in the stm-1 #2 stream (id[15:8]). itmf[2] is enabled by setting the corresponding itmfen register bit high. when itmfen bit is low, the path overhead h4 byte is used to determine tributary multiframe boundaries. itmf[2] is selectable to pulse high during the third byte after j1 of the first frame of the tributary multiframe or during the h4 byte which indicates that the next frame is the first frame of the tributary multiframe. selection between marking each h4 or the third byte after each j1 is controlled by the corresponding itmfh4 register bit. pulses on itmf[2] are only effective during the h4 or third byte after each j1 byte positions, as appropriate. when itmfh4 is low, itmf[2] can be set high for the entire first frame of the tributary multiframe. itmf[2] must be low for the 2 nd , 3 rd , and 4 th frame of the tributary multiframe. when itmfh4 is high, itmf[2] can be set high for the entire fourth frame of the tributary multiframe. itmf[2] must be low for the 1 st , 2 nd and 3 rd frame of the tributary multiframe. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), itmf[2] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), itmf[2] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 29 pin name type pin no. function itmf[3] input aa20 the active high incoming tributary multiframe #3 (itmf[3]) signal identifies the first frame of the tributary multiframe for each sts-1 synchronous payload envelope, au3, or au4 administrative unit in the stm-1 #3 stream (id[23:16]). itmf[3] is enabled by setting the corresponding itmfen register bit high. when itmfen bit is low, the path overhead h4 byte is used to determine tributary multiframe boundaries. itmf[3] is selectable to pulse high during the third byte after j1 of the first frame of the tributary multiframe or during the h4 byte which indicates that the next frame is the first frame of the tributary multiframe. selection between marking each h4 or the third byte after each j1 is controlled by the corresponding itmfh4 register bit. pulses on itmf[3] are only effective during the h4 or third byte after each j1 byte positions, as appropriate. when itmfh4 is low, itmf[3] can be set high for the entire first frame of the tributary multiframe. itmf[3] must be low for the 2 nd , 3 rd , and 4 th frame of the tributary multiframe. when itmfh4 is high, itmf[3] can be set high for the entire fourth frame of the tributary multiframe. itmf[3] must be low for the 1 st , 2 nd and 3 rd frame of the tributary multiframe. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), itmf[3] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), itmf[3] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 30 pin name type pin no. function itmf[4] input ac5 the active high incoming tributary multiframe #4 (itmf[4]) signal identifies the first frame of the tributary multiframe for each sts-1 synchronous payload envelope, au3, or au4 administrative unit in the stm-1 #4 stream (id[31:24]). itmf[4] is enabled by setting the corresponding itmfen register bit high. when itmfen bit is low, the path overhead h4 byte is used to determine tributary multiframe boundaries. itmf[4] is selectable to pulse high during the third byte after j1 of the first frame of the tributary multiframe or during the h4 byte which indicates that the next frame is the first frame of the tributary multiframe. selection between marking each h4 or the third byte after each j1 is controlled by the corresponding itmfh4 register bit. pulses on itmf[4] are only effective during the h4 or third byte after each j1 byte positions, as appropriate. when itmfh4 is low, itmf[4] can be set high for the entire first frame of the tributary multiframe. itmf[4] must be low for the 2 nd , 3 rd , and 4 th frame of the tributary multiframe. when itmfh4 is high, itmf[4] can be set high for the entire fourth frame of the tributary multiframe. itmf[4] must be low for the 1 st , 2 nd and 3 rd frame of the tributary multiframe. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), itmf[4] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), itmf[4] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 31 pin name type pin no. function itpl[1] input w2 the incoming tributary payload active #1 (itpl[1]) signal marks the bytes carrying the tributary payload for the stm-4 or stm-1 #1 stream when pointer interpreter bypass is enabled (pibyp bit set high). when pointer interpreter bypass is disabled (pibyp bit set low), itpl[1] is ignored. also, itpl[1] is ignored when ipl[1] is low. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), itpl[1] is set high to mark each tributary payload byte of the stm-1 #1 stream on the id[7:0] bus. itpl[1] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), itpl[1] is set high to mark each tributary payload byte of the stm-4 stream on the id[7:0] bus. itpl[1] is sampled on the rising edge of hsclk. itpl[2] input b19 the incoming tributary payload active #2 (itpl[2]) signal marks the bytes carrying the tributary payload for the stm-1 #2 stream when pointer interpreter bypass is enabled (pibyp bit set high). when pointer interpreter bypass is disabled (pibyp bit set low), itpl[2] is ignored. also, itpl[2] is ignored when ipl[2] is low. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), itpl[2] is set high to mark each tributary payload byte on the id[15:8] bus. itpl[2] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), itpl[2] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 32 pin name type pin no. function itpl[3] input w20 the incoming tributary payload active #3 (itpl[3]) signal marks the bytes carrying the tributary payload for the stm-1 #3 stream when pointer interpreter bypass is enabled (pibyp bit set high). when pointer interpreter bypass is disabled (pibyp bit set low), itpl[3] is ignored. also, itpl[3] is ignored when ipl[3] is low. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), itpl[3] is set high to mark each tributary payload byte on the id[23:16] bus. itpl[3] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), itpl[3] is unused and must be strapped low. itpl[4] input aa7 the incoming tributary payload active #4 (itpl[4]) signal marks the bytes carrying the tributary payload for the stm-1 #4 stream when pointer interpreter bypass is enabled (pibyp bit set high). when pointer interpreter bypass is disabled (pibyp bit set low), itpl[4] is ignored. also, itpl[4] is ignored when ipl[4] is low. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), itpl[4] is set high to mark each tributary payload byte on the id[31:24] bus. itpl[4] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), itpl[4] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 33 pin name type pin no. function itv5[1] input v3 the incoming tributary v5 byte #1 (itv5[1]) signal marks the tributary v5 bytes of the stm-4 or stm-1 #1 stream when pointer interpreter bypass is enabled (pibyp bit set high). when pointer interpreter bypass is disabled (pibyp bit set low), itv5[1] is ignored. also, itv5[1] is ignored when ipl[1] is low. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), itv5[1] is set high to mark each tributary v5 byte of the stm-1 #1 stream on the id[7:0] bus. when the incoming tributary is a tu3, itv5[1] marks the j1 byte of the tu3. itv5[1] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), itv5[1] is set high to mark each tributary v5 byte of the stm-4 stream on the id[7:0] bus. when the incoming tributary is a tu3, itv5[1] marks the j1 byte of the tu3. itv5[1] is sampled on the rising edge of hsclk.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 34 pin name type pin no. function itv5[2] input c18 the incoming tributary v5 byte #2 (itv5[2]) signal marks the tributary v5 bytes of the stm-1 #2 stream when pointer interpreter bypass is enabled (pibyp bit set high). when pointer interpreter bypass is disabled (pibyp bit set low), itv5[2] is ignored. also, itv5[2] is ignored when ipl[2] is low. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), itv5[2] is set high to mark each tributary v5 byte on the id[15:8] bus. when the incoming tributary is a tu3, itv5[2] marks the j1 byte of the tu3. itv5[2] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), itv5[2] is unused and must be strapped low. itv5[3] input y21 the incoming tributary v5 byte #3 (itv5[3]) signal marks the tributary v5 bytes of the stm-1 #3 stream when pointer interpreter bypass is enabled (pibyp bit set high). when pointer interpreter bypass is disabled (pibyp bit set low), itv5[3] is ignored. also, itv5[3] is ignored when ipl[3] is low. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), itv5[3] is set high to mark each tributary v5 byte on the id[23:16] bus. when the incoming tributary is a tu3, itv5[3] marks the j1 byte of the tu3. itv5[3] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), itv5[3] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 35 pin name type pin no. function itv5[4] input ab6 the incoming tributary v5 byte #4 (itv5[4]) signal marks the tributary v5 bytes of the stm-1 #4 stream when pointer interpreter bypass is enabled (pibyp bit set high). when pointer interpreter bypass is disabled (pibyp bit set low), itv5[4] is ignored. also, itv5[4] is ignored when ipl[4] is low. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), itv5[4] is set high to mark each tributary v5 byte on the id[31:24] bus. when the incoming tributary is a tu3, itv5[4] marks the j1 byte of the tu3. itv5[4] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), itv5[4] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 36 pin name type pin no. function iais[1] input y1 the incoming tributary alarm indication signal #1 (iais[1]) marks tributaries on the incoming stm- 4 or stm-1 #1 stream that are in ais state when pointer interpreter bypass is enabled (pibyp bit set high). when pointer interpreter bypass is disabled (pibyp bit set low), iais[1] is ignored. also, iais[1] is ignored when ipl[1] is low. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), iais[1] is set high when the associated tributary of the stm-1 #1 stream on the id[7:0] is in ais state and is set low when the associated tributary is operating normally. iais[1] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), iais[1] is set high when the associated tributary of the stm-4 stream on the id[7:0] is in ais state and is set low when the associated tributary is operating normally. iais[1] is sampled on the rising edge of hsclk.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 37 pin name type pin no. function iais[2] input a20 the incoming tributary alarm indication signal #2 (iais[2]) marks tributaries on the incoming stm- stm-1 #2 stream that are in ais state when pointer interpreter bypass is enabled (pibyp bit set high). when pointer interpreter bypass is disabled (pibyp bit set low), iais[2] is ignored. also, iais[2] is ignored when ipl[2] is low. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), iais[2] is set high when the associated tributary on the id[15:8] is in ais state and is set low when the associated tributary is operating normally. iais[2] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), iais[2] is unused and must be strapped low. iais[3] input aa23 the incoming tributary alarm indication signal #3 (iais[3]) marks tributaries on the incoming stm- stm-1 #3 stream that are in ais state when pointer interpreter bypass is enabled (pibyp bit set high). when pointer interpreter bypass is disabled (pibyp bit set low), iais[3] is ignored. also, iais[3] is ignored when ipl[3] is low. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), iais[3] is set high when the associated tributary on the id[23:16] is in ais state and is set low when the associated tributary is operating normally. iais[3] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), iais[3] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 38 pin name type pin no. function iais[4] input y8 the incoming tributary alarm indication signal #4 (iais[4]) marks tributaries on the incoming stm- stm-1 #4 stream that are in ais state when pointer interpreter bypass is enabled (pibyp bit set high). when pointer interpreter bypass is disabled (pibyp bit set low), iais[4] is ignored. also, iais[4] is ignored when ipl[4] is low. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), iais[4] is set high when the associated tributary on the id[31:24] is in ais state and is set low when the associated tributary is operating normally. iais[4] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), iais[4] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 39 pin name type pin no. function idp[1] input w1 the incoming data parity #1 (idp[1]) signal carries the parity of the incoming signals for the stm-4 or stm-1 #1 stream. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), the parity calculation encompasses the id[7:0] bus and optionally the ic1j1[1] and the ipl[1] signals. ic1j1[1] and ipl[1] can be included in the parity calculation by setting the corresponding incic1j1 and incipl register bits high, respectively. odd parity is selected by setting the corresponding iop register bit high, and even parity is selected by setting the iop bit low. idp[1] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), the parity calculation encompasses the id[7:0] bus and optionally the ic1j1[1] and the ipl[1] signals. ic1j1[1] and ipl[1] can be included in the parity calculation by setting the corresponding incic1j1 and incipl register bits high, respectively. odd parity is selected by setting the corresponding iop register bit high, and even parity is selected by setting the iop bit low. idp[1] is sampled on the rising edge of hsclk.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 40 pin name type pin no. function idp[2] input a19 the incoming data parity #2 (idp[2]) signal carries the parity of the incoming signals for the stm-1 #2 stream. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), the parity calculation encompasses the id[15:8] bus and optionally the ic1j1[2] and the ipl[2] signals. ic1j1[2] and ipl[2] can be included in the parity calculation by setting the corresponding incic1j1 and incipl register bits high, respectively. odd parity is selected by setting the corresponding iop register bit high, and even parity is selected by setting the iop bit low. idp[2] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), idp[2] is unused and must be strapped low. idp[3] input y19 the incoming data parity #3 (idp[3]) signal carries the parity of the incoming signals for the stm-1 #3 stream. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), the parity calculation encompasses the id[23:16] bus and optionally the ic1j1[3] and the ipl[3] signals. ic1j1[3] and ipl[3] can be included in the parity calculation by setting the corresponding incic1j1 and incipl register bits high, respectively. odd parity is selected by setting the corresponding iop register bit high, and even parity is selected by setting the iop bit low. idp[3] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), idp[3] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 41 pin name type pin no. function idp[4] input aa6 the incoming data parity #4 (idp[4]) signal carries the parity of the incoming signals for the stm-1 #4 stream. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), the parity calculation encompasses the id[31:24] bus and optionally the ic1j1[4] and the ipl[4] signals. ic1j1[4] and ipl[4] can be included in the parity calculation by setting the corresponding incic1j1 and incipl register bits high, respectively. odd parity is selected by setting the corresponding iop register bit high, and even parity is selected by setting the iop bit low. idp[4] is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), idp[4] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 42 pin name type pin no. function id[0] id[1] id[2] id[3] id[4] id[5] id[6] id[7] input r2 r3 t2 u1 t3 t4 u3 v2 the incoming data bus (id[7:0]) carries the stm-4 or stm-1 #1 sonet/sdh frame data in byte serial format. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), the id[7:0] bus carries the stm-1 #1 stream. id[7] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. id[0] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. the id[7:0] bus is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), the id[7:0] bus carries the stm-4 stream. id[7] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. id[0] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. the id[7:0] bus is sampled on the rising edge of hsclk. id[8] id[9] id[10] id[11] id[12] id[13] id[14] id[15] input b15 c15 b16 c16 a17 d16 c17 b18 the incoming data bus (id[15:8]) carries the stm-1 #2 sonet/sdh frame data in byte serial format. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), id[15] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. id[8] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. the id[15:8] bus is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), the id[15:8] bus is unused and all bus signals must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 43 pin name type pin no. function id[16] id[17] id[18] id[19] id[20] id[21] id[22] id[23] input ac19 y17 aa18 ab19 ac20 aa19 ab20 ac21 the incoming data bus (id[23:16]) carries the stm-1 #3 sonet/sdh frame data in byte serial format. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), id[23] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. id[16] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. the id[23:16] bus is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), the id[23:16] bus is unused and all bus signals must be strapped low. id[24] id[25] id[26] id[27] id[28] id[29] id[30] id[31] input y3 aa4 y5 ac3 ab4 aa5 ac4 ab5 the incoming data bus (id[31:24]) carries the stm-1 #4 sonet/sdh frame data in byte serial format. in incoming stm-1 (sts-3) interface mode (ihsmodeb set high), id[31] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. id[24] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. the id[31:24] bus is sampled on the rising edge of sclk. in incoming stm-4 (sts-12) interface mode (ihsmodeb set low), the id[31:24] bus is unused and all bus signals must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 44 pin name type pin no. function gsclk_fp input j1 the active high generated system clock frame position (gsclk_fp) signal aligns the hsclk divide by four logic which generates the gsclk[1:0] signals when stm-4 (sts-12) interface mode is selected at the incoming or outgoing interface (ihsmodeb or ohsmodeb set low). gsclk_fp should be set high for one hsclk period at an interval of four or multiples of four hsclk periods. gsclk_fp is sampled on the rising edge of hsclk. otmf[1] input j2 the active high outgoing tributary multiframe #1 (otmf[1]) signal identifies the first frame of the tributary multiframe for each au3, or au4 administrative unit, or sts-1 synchronous payload envelope in the outgoing stm-4 or stm-1 #1 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), the otmf[1] identifies the first frame of the tributary multiframe in the stm-1 stream on the od[7:0] bus. otmf[1] is selectable to pulse high during the third byte after j1 of the first sts-1 stream or during the h4 byte of the path overhead which indicates that the next frame is the first frame of the tributary multiframe. selection between marking the third byte after each j1 or h4 bytes is controlled by the corresponding otmfh4 register bit. pulses on otmf[1] are only effective during the h4 or third byte after each j1 byte positions, as appropriate. otmf[1] is ignored at other byte positions. otmf[1] is sampled on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), the otmf[1] identifies
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 45 pin name type pin no. function the first frame of the tributary multiframe in each stm-1 within the stm-4 (od[7:0]) stream. otmf[1] is selectable to pulse high during the third byte after j1 of the first sts-1 in each stm-1 or during the h4 byte of the path overhead which indicates that the next frame is the first frame of the tributary multiframe. selection between marking the third byte after each j1 or h4 bytes is controlled by the corresponding otmfh4 register bit. pulses on otmf[1] are only effective during the h4 or third byte after each j1 byte positions, as appropriate. otmf[1] is ignored at other byte positions. otmf[1] is sampled on the rising edge of hsclk.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 46 pin name type pin no. function otmf[2] input d23 the active high outgoing tributary multiframe #2 (otmf[2]) signal identifies the first frame of the tributary multiframe for each au3, or au4 administrative unit, or sts-1 synchronous payload envelope in the outgoing stm-1 #2 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), the otmf[2] identifies the first frame of the tributary multiframe in the stm-1 stream on the od[15:8] bus. otmf[2] is selectable to pulse high during the third byte after j1 of the first sts-1 stream or during the h4 byte of the path overhead which indicates that the next frame is the first frame of the tributary multiframe. selection between marking the third byte after each j1 or h4 bytes is controlled by the corresponding otmfh4 register bit. pulses on otmf[2] are only effective during the h4 or third byte after each j1 byte positions, as appropriate. otmf[2] is ignored at other byte positions. otmf[2] is sampled on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), the otmf[2] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 47 pin name type pin no. function otmf[3] input l21 the active high outgoing tributary multiframe #3 (otmf[3]) signal identifies the first frame of the tributary multiframe for each au3, or au4 administrative unit, or sts-1 synchronous payload envelope in the outgoing stm-1 #3 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), the otmf[3] identifies the first frame of the tributary multiframe in the stm-1 stream on the od[23:16] bus. otmf[3] is selectable to pulse high during the third byte after j1 of the first sts-1 stream or during the h4 byte of the path overhead which indicates that the next frame is the first frame of the tributary multiframe. selection between marking the third byte after each j1 or h4 bytes is controlled by the corresponding otmfh4 register bit. pulses on otmf[3] are only effective during the h4 or third byte after each j1 byte positions, as appropriate. otmf[3] is ignored at other byte positions. otmf[3] is sampled on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), the otmf[3] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 48 pin name type pin no. function otmf[4] input aa11 the active high outgoing tributary multiframe #4 (otmf[4]) signal identifies the first frame of the tributary multiframe for each au3, or au4 administrative unit, or sts-1 synchronous payload envelope in the outgoing stm-1 #4 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), the otmf[4] identifies the first frame of the tributary multiframe in the stm-1 stream on the od[31:24] bus. otmf[4] is selectable to pulse high during the third byte after j1 of the first sts-1 stream or during the h4 byte of the path overhead which indicates that the next frame is the first frame of the tributary multiframe. selection between marking the third byte after each j1 or h4 bytes is controlled by the corresponding otmfh4 register bit. pulses on otmf[4] are only effective during the h4 or third byte after each j1 byte positions, as appropriate. otmf[4] is ignored at other byte positions. otmf[4] is sampled on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), the otmf[4] is unused and must be strapped low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 49 pin name type pin no. function cout[1] output j3 the controlled output signal #1 (cout[1]) is a software programmable output that is controlled by the coutx register bit associated with each tributary in the stm-4 or stm-1 #1 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), cout[1] is synchronized to the stm-1 #1 stream on od[7:0] bus. cout[1] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), cout[1] is synchronized to the stm-4 stream on od[7:0] bus. cout[1] is updated on the rising edge of hsclk. cout[2] output l20 the controlled output signal #2 (cout[2]) is a software programmable output that is controlled by the coutx register bit associated with each tributary in the stm-1 #2 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), cout[2] is synchronized to the od[15:8] bus. cout[2] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), cout[2] is invalid. cout[3] output u23 the controlled output signal #3 (cout[3]) is a software programmable output that is controlled by the coutx register bit associated with each tributary in the stm-1 #3 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), cout[3] is synchronized to the od[23:16] bus. cout[3] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), cout[3] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 50 pin name type pin no. function cout[4] output aa16 the controlled output signal #4 (cout[4]) is a software programmable output that is controlled by the coutx register bit associated with each tributary in the stm-1 #4 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), cout[4] is synchronized to the od[31:24] bus. cout[4] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), cout[4] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 51 pin name type pin no. function od[0] od[1] od[2] od[3] od[4] od[5] od[6] od[7] output c1 d2 e3 d1 e2 f3 g4 e1 the outgoing data bus (od[7:0]) carries the stm-4 or stm-1 #1 sonet/sdh frame data in byte serial format. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), the od[7:0] bus carries the stm-1 #1 stream. od[7] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. od[0] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. od[7:0] is set to all-zeros at transport overhead bytes, except for the a1 and a2 framing bytes and the h1 and h2 pointer bytes. pointer offset is determined by the stp outgoing pointer msb and lsb registers. the od[7:0] bus is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), the id[7:0] bus carries the stm-4 stream. od[7] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. od[0] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. od[7:0] is set to all-zeros at transport overhead bytes, except for the a1 and a2 framing bytes and the h1 and h2 pointer bytes. pointer offset is determined by the stp outgoing pointer msb and lsb registers. the od[7:0] bus is updated on the rising edge of hsclk.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 52 pin name type pin no. function od[8] od[9] od[10] od[11] od[12] od[13] od[14] od[15] output e23 f22 g21 h20 g22 h21 g23 h22 the outgoing data bus (od[15:8]) carries the stm-1 #2 sonet/sdh frame data in byte serial format. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), od[15] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. od[8] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. od[15:8] is set to all-zeros at transport overhead bytes, except for the a1 and a2 framing bytes and the h1 and h2 pointer bytes. pointer offset is determined by the stp outgoing pointer msb and lsb registers. the od[15:8] bus is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), the od[15:8] bus is unused and all bus signals are invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 53 pin name type pin no. function od[16] od[17] od[18] od[19] od[20] od[21] od[22] od[23] output m22 m21 n23 n21 n20 p23 p22 p21 the outgoing data bus (od[23:16]) carries the stm-1 #3 sonet/sdh frame data in byte serial format. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), od[23] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. od[16] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. od[23:16] is set to all-zeros at transport overhead bytes, except for the a1 and a2 framing bytes and the h1 and h2 pointer bytes. pointer offset is determined by the stp outgoing pointer msb and lsb registers. the od[23:16] bus is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), the od[23:16] bus is unused and all bus signals are invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 54 pin name type pin no. function od[24] od[25] od[26] od[27] od[28] od[29] od[30] od[31] output aa12 ab12 ac13 aa13 y13 ac14 ab14 aa14 the outgoing data bus (od[31:24]) carries the stm-1 #4 sonet/sdh frame data in byte serial format. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), od[31] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. od[24] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. od[31:24] is set to all-zeros at transport overhead bytes, except for the a1 and a2 framing bytes and the h1 and h2 pointer bytes. pointer offset is determined by the stp outgoing pointer msb and lsb registers. the od[31:24] bus is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), the od[31:24] bus is unused and all bus signals are invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 55 pin name type pin no. function odp[1] output f2 the outgoing data parity #1 (odp[1]) signal carries the parity of the outgoing stm-4 or stm- 1 #1 data stream on od[7:0] and optionally including the oc1j1v1[1] and the opl[1] signals. oc1j1v1[1] and opl[1] can be included in the parity calculation by setting the corresponding incoc1j1 and incopl register bits high, respectively. odd parity is selected by setting the corresponding oop register bit high, and even parity is selected by setting the oop bit low. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), odp[1] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), odp[1] is updated on the rising edge of hsclk. odp[2] output j21 the outgoing data parity #2 (odp[2]) signal carries the parity of the outgoing stm-1 #2 data stream on od[15:8] and optionally including the oc1j1v1[2] and the opl[2] signals. oc1j1v1[2] and opl[2] can be included in the parity calculation by setting the corresponding incoc1j1 and incopl register bits high, respectively. odd parity is selected by setting the corresponding oop register bit high, and even parity is selected by setting the oop bit low. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), odp[2] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), odp[2] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 56 pin name type pin no. function odp[3] output r23 the outgoing data parity #3 (odp[3]) signal carries the parity of the outgoing stm-1 #3 data stream on od[23:16] and optionally including the oc1j1v1[3] and the opl[3] signals. oc1j1v1[3] and opl[3] can be included in the parity calculation by setting the corresponding incoc1j1 and incopl register bits high, respectively. odd parity is selected by setting the corresponding oop register bit high, and even parity is selected by setting the oop bit low. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), odp[3] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), odp[3] is invalid. odp[4] output ac15 the outgoing data parity #4 (odp[4]) signal carries the parity of the outgoing stm-1 #4 data stream on od[31:24] and optionally including the oc1j1v1[4] and the opl[4] signals. oc1j1v1[4] and opl[4] can be included in the parity calculation by setting the corresponding incoc1j1 and incopl register bits high, respectively. odd parity is selected by setting the corresponding oop register bit high, and even parity is selected by setting the oop bit low. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), odp[4] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), odp[4] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 57 pin name type pin no. function otpl[1] output h4 the outgoing tributary payload active #1 (otpl[1]) signal marks the bytes carrying the tributary payload for the stm-4 or stm-1 #1 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), otpl[1] is set high to mark each tributary payload byte of the stm-1 #1 stream on the od[7:0] bus. otpl[1] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), otpl[1] is set high to mark each tributary payload byte of the stm-4 stream on the od[7:0] bus. otpl[1] is updated on the rising edge of hsclk. otpl[2] output j23 the outgoing tributary payload active #2 (otpl[2]) signal marks the bytes carrying the tributary payload for the stm-1 #2 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), otpl[2] is set high to mark each tributary payload byte on the od[15:8] bus. otpl[2] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), otpl[2] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 58 pin name type pin no. function otpl[3] output r22 the outgoing tributary payload active #3 (otpl[3]) signal marks the bytes carrying the tributary payload for the stm-1 #3 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), otpl[3] is set high to mark each tributary payload byte on the od[23:16] bus. otpl[3] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), otpl[3] is invalid. otpl[4] output ab15 the outgoing tributary payload active #4 (otpl[4]) signal marks the bytes carrying the tributary payload for the stm-1 #4 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), otpl[4] is set high to mark each tributary payload byte on the od[31:24] bus. otpl[4] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), otpl[4] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 59 pin name type pin no. function otv5[1] output g3 the outgoing tributary v5 byte #1 (otv5[1]) signal marks the tributary v5 bytes of the stm-4 or stm-1 #1 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), otv5[1] is set high to mark each tributary v5 byte of the stm-1 #1 stream on the od[7:0] bus. when the outgoing tributary is a tu3, otv5[1] marks the j1 byte of the tu3. otv5[1] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), otv5[1] is set high to mark each tributary v5 byte of the stm-4 stream on the od[7:0] bus. when the outgoing tributary is a tu3, otv5[1] marks the j1 byte of the tu3. otv5[1] is updated on the rising edge of hsclk. otv5[2] output k20 the outgoing tributary v5 byte #2 (otv5[2]) signal marks the tributary v5 bytes of the stm-1 #2 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), otv5[2] is set high to mark each tributary v5 byte on the od[15:8] bus. when the outgoing tributary is a tu3, otv5[2] marks the j1 byte of the tu3. otv5[2] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), otv5[2] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 60 pin name type pin no. function otv5[3] output p20 the outgoing tributary v5 byte #3 (otv5[3]) signal marks the tributary v5 bytes of the stm-1 #3 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), otv5[3] is set high to mark each tributary v5 byte on the od[23:16] bus. when the outgoing tributary is a tu3, otv5[3] marks the j1 byte of the tu3. otv5[3] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), otv5[3] is invalid. otv5[4] output y14 the outgoing tributary v5 byte #4 (otv5[4]) signal marks the tributary v5 bytes of the stm-1 #4 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), otv5[4] is set high to mark each tributary v5 byte on the od[31:24] bus. when the outgoing tributary is a tu3, otv5[4] marks the j1 byte of the tu3. otv5[4] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), otv5[4] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 61 pin name type pin no. function ais[1] output g1 the tributary alarm indication signal output #1 (ais[1]) marks tributaries on the outgoing stm-4 or stm-1 #1 stream that are in ais state. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), ais[1] is set high when ais is inserted in the associated tributary of the stm-1 #1 stream on the od[7:0] and is set low when the ais is not inserted. ais[1] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), ais[1] is set high when ais is inserted in the associated tributary of the stm-4 stream on the od[7:0] and is set low when the ais is not inserted. ais[1] is set low for transport overhead bytes. ais[1] is updated on the rising edge of hsclk. ais[2] output k21 the tributary alarm indication signal output #2 (ais[2]) marks tributaries on the outgoing stm-4 or stm-1 #2 stream that are in ais state. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), ais[2] is set high when ais is inserted in the associated tributary on the od[15:8] and is set low when the ais is not inserted. ais[2] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), ais[2] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 62 pin name type pin no. function ais[3] output r21 the tributary alarm indication signal output #3 (ais[3]) marks tributaries on the outgoing stm-4 or stm-1 #3 stream that are in ais state. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), ais[3] is set high when ais is inserted in the associated tributary on the od[23:16] and is set low when the ais is not inserted. ais[3] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), ais[3] is invalid. ais[4] output aa15 the tributary alarm indication signal output #4 (ais[4]) marks tributaries on the outgoing stm-4 or stm-1 #4 stream that are in ais state. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), ais[4] is set high when ais is inserted in the associated tributary on the od[31:24] and is set low when the ais is not inserted. ais[4] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), ais[4] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 63 pin name type pin no. function idle[1] output h3 the tributary idle indication signal output #1 (idle[1]) marks tributaries on the outgoing stm- 4 or stm-1 #1 stream that are in idle state. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), idle[1] is set high when idle code is inserted in the associated tributary of the stm-1 #1 stream on the od[7:0] and is set low when the idle code is not inserted. idle[1] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), idle[1] is set high when idle code is inserted in the associated tributary of the stm-4 stream on the od[7:0] and is set low when the idle code is not inserted. idle[1] is updated on the rising edge of hsclk. idle[2] output k22 the tributary idle indication signal output #2 (idle[2]) marks tributaries on the outgoing stm- 1 #2 stream that are in idle state. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), idle[2] is set high when idle code is inserted in the associated tributary on the od[15:8] and is set low when the idle code is not inserted. idle[2] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), idle[2] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 64 pin name type pin no. function idle[3] output t22 the tributary idle indication signal output #3 (idle[3]) marks tributaries on the outgoing stm- 1 #3 stream that are in idle state. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), idle[3] is set high when idle code is inserted in the associated tributary on the od[23:16] and is set low when the idle code is not inserted. idle[3] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), idle[3] is invalid. idle[4] output ab16 the tributary idle indication signal output #4 (idle[4]) marks tributaries on the outgoing stm- 1 #4 stream that are in idle state. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), idle[4] is set high when idle code is inserted in the associated tributary on the od[31:24] and is set low when the idle code is not inserted. idle[4] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), idle[4] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 65 pin name type pin no. function tpoh[1] output h2 the outgoing tributary path overhead byte #1 (tpoh[1]) signal marks the tributary path overhead bytes in the outgoing stm-4 or stm-1 #1 stream. for streams in tu3 mode, the j1, b3, c2, g1, f2, h4, z3, z4 and z5 bytes are marked. for streams out of tu3 mode, v5, j2, z6 an z7 bytes are marked. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), tpoh[1] is set high to mark each tributary path overhead byte of the stm-1 #1 stream on the od[7:0] bus. tpoh[1] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), tpoh[1] is set high to mark each tributary path overhead byte of the stm-4 stream on the od[7:0] bus. tpoh[1] is set low for transport overhead bytes. tpoh[1] is updated on the rising edge of hsclk. tpoh[2] output k23 the outgoing tributary path overhead byte #2 (tpoh[2]) signal marks the tributary path overhead bytes in the outgoing stm-1 #2 stream. for streams in tu3 mode, the j1, b3, c2, g1, f2, h4, z3, z4 and z5 bytes are marked. for streams out of tu3 mode, v5, j2, z6 an z7 bytes are marked. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), tpoh[2] is set high to mark each tributary path overhead byte on the od[15:8] bus. tpoh[2] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), tpoh[2] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 66 pin name type pin no. function tpoh[3] output t21 the outgoing tributary path overhead byte #3 (tpoh[3]) signal marks the tributary path overhead bytes in the outgoing stm-1 #3 stream. for streams in tu3 mode, the j1, b3, c2, g1, f2, h4, z3, z4 and z5 bytes are marked. for streams out of tu3 mode, v5, j2, z6 an z7 bytes are marked. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), tpoh[3] is set high to mark each tributary path overhead byte on the od[23:16] bus. tpoh[3] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), tpoh[3] is invalid. tpoh[4] output ac17 the outgoing tributary path overhead byte #4 (tpoh[4]) signal marks the tributary path overhead bytes in the outgoing stm-1 #4 stream. for streams in tu3 mode, the j1, b3, c2, g1, f2, h4, z3, z4 and z5 bytes are marked. for streams out of tu3 mode, v5, j2, z6 an z7 bytes are marked. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), tpoh[4] is set high to mark each tributary path overhead byte on the od[31:24] bus. tpoh[4] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), tpoh[4] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 67 pin name type pin no. function oc1j1v1[1] output d3 the outgoing composite frame pulse #1 (oc1j1v1[1]) marks the transport, synchronous payload envelope and tributary multiframe frame boundaries on the outgoing stm-4 or stm-1 #1 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), oc1j1v1[1] pulses high to mark the first c1 byte of the stm-1 #1 transport envelope frame on the od[7:0] bus. it also pulses high to mark the j1 byte(s). when au3/tug3 bypass is disabled (tugen set high and tugbyp set low), the au3/au4 pointer offset (j1 position relative to c1) is determined by the corresponding stp outgoing pointer msb and lsb registers. optionally, oc1j1v1[1] also marks the third byte after j1 of the first tributary in each sts-1 (tug3) stream when the corresponding ov1en register bit is set high. when au3/tug3 bypass is enabled (tugen set low or tugbyp set high), the j1 and v1 byte position pulses are delayed versions from the ic1j1[1] input. oc1j1v1[1] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), oc1j1v1[1] pulses high to mark the first c1 byte of the stm-4 transport envelope frame on the od[7:0] bus. it also pulses high to mark the stm-1 j1 bytes. when au3/tug3 bypass is disabled (tugen set high and tugbyp set low), the au3/au4 pointer offset (j1 position relative to c1) of each stm-1 is determined by the corresponding stp outgoing pointer msb and lsb registers. optionally, oc1j1v1[1] also marks the third byte after j1 of the first tributary in each sts-1 (tug3) stream when the corresponding ov1en
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 68 pin name type pin no. function register bit is set high. when au3/tug3 bypass is enabled (tugen set low or tugbyp set high), the j1 and v1 byte position pulses are delayed versions from the ic1j1[1] input. oc1j1v1[1] is updated on the rising edge of hsclk. oc1j1v1[2] output f21 the outgoing composite frame pulse #2 (oc1j1v1[2]) marks the transport, synchronous payload envelope and tributary multiframe frame boundaries on the outgoing stm-1 #2 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), oc1j1v1[2] pulses high to mark the first c1 byte of the stm-1 #2 transport envelope frame on the od[15:8] bus. it also pulses high to mark the j1 byte(s). when au3/tug3 bypass is disabled (tugen set high and tugbyp set low), the au3/au4 pointer offset (j1 position relative to c1) is determined by the corresponding stp outgoing pointer msb and lsb registers. optionally, oc1j1v1[2] also marks the third byte after j1 of the first tributary in each sts-1 (tug3) stream when the corresponding ov1en register bit is set high. when au3/tug3 bypass is enabled (tugen set low or tugbyp set high), the j1 and v1 byte position pulses are delayed versions from the ic1j1[2] input. oc1j1v1[2] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), oc1j1v1[2] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 69 pin name type pin no. function oc1j1v1[3] output l22 the outgoing composite frame pulse #3 (oc1j1v1[3]) marks the transport, synchronous payload envelope and tributary multiframe frame boundaries on the outgoing stm-1 #3 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), oc1j1v1[3] pulses high to mark the first c1 byte of the stm-1 #3 transport envelope frame on the od[23:16] bus. it also pulses high to mark the j1 byte(s). when au3/tug3 bypass is disabled (tugen set high and tugbyp set low), the au3/au4 pointer offset (j1 position relative to c1) is determined by the corresponding stp outgoing pointer msb and lsb registers. optionally, oc1j1v1[3] also marks the third byte after j1 of the first tributary in each sts-1 (tug3) stream when the corresponding ov1en register bit is set high. when au3/tug3 bypass is enabled (tugen set low or tugbyp set high), the j1 and v1 byte position pulses are delayed versions from the ic1j1[3] input. oc1j1v1[3] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), oc1j1v1[3] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 70 pin name type pin no. function oc1j1v1[4] output ab11 the outgoing composite frame pulse #4 (oc1j1v1[4]) marks the transport, synchronous payload envelope and tributary multiframe frame boundaries on the outgoing stm-1 #4 stream. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), oc1j1v1[4] pulses high to mark the first c1 byte of the stm-1 #4 transport envelope frame on the od[31:24] bus. it also pulses high to mark the j1 byte(s). when au3/tug3 bypass is disabled (tugen set high and tugbyp set low), the au3/au4 pointer offset (j1 position relative to c1) is determined by the corresponding stp outgoing pointer msb and lsb registers. optionally, oc1j1v1[4] also marks the third byte after j1 of the first tributary in each sts-1 (tug3) stream when the corresponding ov1en register bit is set high. when au3/tug3 bypass is enabled (tugen set low or tugbyp set high), the j1 and v1 byte position pulses are delayed versions from the ic1j1[4] input. oc1j1v1[4] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), oc1j1v1[4] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 71 pin name type pin no. function opl[1] output e4 the outgoing payload active #1 (opl[1]) signal identifies synchronous payload envelope bytes on the outgoing stm-4 or stm-1 #1 stream. when au3/tug3 bypass is disabled (tugen set high and tugbyp set low), opl[1] is set high to mark synchronous payload envelop bytes and set low to mark transport overhead bytes. when au3/tug3 bypass is enabled (tugen set low or tugbyp set high), opl[1] is a delayed version of ipl[1]. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), opl[1] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), opl[1] is updated on the rising edge of hsclk. opl[2] output g20 the outgoing payload active #2 (opl[2]) signal identifies synchronous payload envelope bytes on the outgoing stm-1 #2 stream. when au3/tug3 bypass is disabled (tugen set high and tugbyp set low), opl[2] is set high to mark synchronous payload envelop bytes and set low to mark transport overhead bytes. when au3/tug3 bypass is enabled (tugen set low or tugbyp set high), opl[2] is a delayed version of ipl[2]. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), opl[2] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), opl[2] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 72 pin name type pin no. function opl[3] output l23 the outgoing payload active #3 (opl[3]) signal identifies synchronous payload envelope bytes on the outgoing stm-1 #3 stream. when au3/tug3 bypass is disabled (tugen set high and tugbyp set low), opl[3] is set high to mark synchronous payload envelop bytes and set low to mark transport overhead bytes. when au3/tug3 bypass is enabled (tugen set low or tugbyp set high), opl[3] is a delayed version of ipl[3]. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), opl[3] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), opl[3] is invalid. opl[4] output ac11 the outgoing payload active #4 (opl[4]) signal identifies synchronous payload envelope bytes on the outgoing stm-1 #4 stream. when au3/tug3 bypass is disabled (tugen set high and tugbyp set low), opl[4] is set high to mark synchronous payload envelop bytes and set low to mark transport overhead bytes. when au3/tug3 bypass is enabled (tugen set low or tugbyp set high), opl[4] is a delayed version of ipl[4]. in outgoing stm-1 (sts-3) interface mode (ohsmodeb set high), opl[4] is updated on the rising edge of sclk. in outgoing stm-4 (sts-12) interface mode (ohsmodeb set low), opl[4] is invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 73 pin name type pin no. function pohck output l2 the tributary path overhead clock (pohck) signal provides timing to sample the extracted tributary path overhead stream and the receive alarm port for stm-1 #1, #2, #3 and #4. pohck is a nominally 9.72 mhz clock. the poh[12:1], pohen[12:1], pohfp[12:1] and rad[4:1] outputs are updated on the falling edge of pohck. poh[1] poh[2] poh[3] output l4 m3 p2 the tributary path overhead (poh[3:1]) signals contain the tributary path overhead bytes (v5, j2, z6 and z7) extracted from the incoming stm-1 #1 stream. poh[1], poh[2] and poh[3] contain the tributary path overhead bytes from sts-1 (au3) #1, #2 and #3, respectively. in au4 mode, poh[1], poh[2] and poh[3] contain the tributary path overhead bytes from tug3 #1, #2 and #3, respectively. all four tributary overhead bytes of each tributary is shifted out once per payload frame. the corresponding pohen signal is set high to identify overhead bytes that are presented for the first time. each poh signal is updated on the falling edge of pohck.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 74 pin name type pin no. function poh[4] poh[5] poh[6] output a21 d21 d22 the tributary path overhead (poh[6:4]) signals contain the tributary path overhead bytes (v5, j2, z6 and z7) extracted from the incoming stm-1 #2 stream. poh[4], poh[5] and poh[6] contain the tributary path overhead bytes from sts-1 (au3) #1, #2 and #3, respectively. in au4 mode, poh[4], poh[5] and poh[6] contain the tributary path overhead bytes from tug3 #1, #2 and #3, respectively. all four tributary overhead bytes of each tributary is shifted out once per payload frame. the corresponding pohen signal is set high to identify overhead bytes that are presented for the first time. each poh signal is updated on the falling edge of pohck. poh[7] poh[8] poh[9] output v22 v21 w21 the tributary path overhead (poh[9:7]) signals contain the tributary path overhead bytes (v5, j2, z6 and z7) extracted from the incoming stm-1 #3 stream. poh[7], poh[8] and poh[9] contain the tributary path overhead bytes from sts-1 (au3) #1, #2 and #3, respectively. in au4 mode, poh[7], poh[8] and poh[9] contain the tributary path overhead bytes from tug3 #1, #2 and #3, respectively. all four tributary overhead bytes of each tributary is shifted out once per payload frame. the corresponding pohen signal is set high to identify overhead bytes that are presented for the first time. each poh signal is updated on the falling edge of pohck.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 75 pin name type pin no. function poh[10] poh[11] poh[12] output ab8 y10 ac10 the tributary path overhead (poh[12:10]) signals contain the tributary path overhead bytes (v5, j2, z6 and z7) extracted from the incoming stm-1 #4 stream. poh[10], poh[11] and poh[12] contain the tributary path overhead bytes from sts-1 (au3) #1, #2 and #3, respectively. in au4 mode, poh[10], poh[11] and poh[12] contain the tributary path overhead bytes from tug3 #1, #2 and #3, respectively. all four tributary overhead bytes of each tributary is shifted out once per payload frame. the corresponding pohen signal is set high to identify overhead bytes that are presented for the first time. each poh signal is updated on the falling edge of pohck. pohfp[1] pohfp[2] pohfp[3] output k1 l1 n1 the tributary path overhead frame pulse (pohfp[3:1]) signals may be used to locate the individual path overhead bits of each tributary for the corresponding sts-1 (tug3) in the incoming stm-1 #1 stream. each pohfp signal is set high to mark bit 1 (the most significant bit) of the v5 byte of the first tributary. pohfp[1], pohfp[2] and pohfp[3] identify frame boundaries of the tributary path overhead bytes from sts-1 (au3) #1, #2 and #3, respectively. in au4 mode, pohfp[1], pohfp[2] and pohfp[3] identify frame boundaries of tug3 #1, #2 and #3, respectively. each pohfp signal is updated on the falling edge of pohck.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 76 pin name type pin no. function pohfp[4] pohfp[5] pohfp[6] output b20 c20 c23 the tributary path overhead frame pulse (pohfp[6:4]) signals may be used to locate the individual path overhead bits of each tributary for the corresponding sts-1 (tug3) in the incoming stm-1 #2 stream. each pohfp signal is set high to mark bit 1 (the most significant bit) of the v5 byte of the first tributary. pohfp[4], pohfp[5] and pohfp[6] identify frame boundaries of the tributary path overhead bytes from sts-1 (au3) #1, #2 and #3, respectively. in au4 mode, pohfp[4], pohfp[5] and pohfp[6] identify frame boundaries of tug3 #1, #2 and #3, respectively. each pohfp signal is updated on the falling edge of pohck. pohfp[7] pohfp[8] pohfp[9] output u21 u20 y23 the tributary path overhead frame pulse (pohfp[9:7]) signals may be used to locate the individual path overhead bits of each tributary for the corresponding sts-1 (tug3) in the incoming stm-1 #3 stream. each pohfp signal is set high to mark bit 1 (the most significant bit) of the v5 byte of the first tributary. pohfp[7], pohfp[8] and pohfp[9] identify frame boundaries of the tributary path overhead bytes from sts-1 (au3) #1, #2 and #3, respectively. in au4 mode, pohfp[7], pohfp[8] and pohfp[9] identify frame boundaries of tug3 #1, #2 and #3, respectively. each pohfp signal is updated on the falling edge of pohck.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 77 pin name type pin no. function pohfp[10] pohfp[11] pohfp[12] output aa8 ab9 aa10 the tributary path overhead frame pulse (pohfp[12:10]) signals may be used to locate the individual path overhead bits of each tributary for the corresponding sts-1 (tug3) in the incoming stm-1 #4 stream. each pohfp signal is set high to mark bit 1 (the most significant bit) of the v5 byte of the first tributary. pohfp[10], pohfp[11] and pohfp[12] identify frame boundaries of the tributary path overhead bytes from sts-1 (au3) #1, #2 and #3, respectively. in au4 mode, pohfp[10], pohfp[11] and pohfp[12] identify frame boundaries of tug3 #1, #2 and #3, respectively. each pohfp signal is updated on the falling edge of pohck. pohen[1] pohen[2] pohen[3] output l3 m2 p3 the tributary path overhead enable (pohen[3:1]) signals may be used to identify tributary path overhead bytes that are being presented on the corresponding poh stream of stm-1 #1 for the first time. each pohen signal is set high when a fresh overhead byte is available on the corresponding poh stream. pohen is set low when the tributary path overhead byte available on the corresponding poh stream has already been shifted out in a previous frame. pohen[1], pohen[2] and pohen[3] identify the status of tributary path overhead bytes from sts-1 (au3) #1, #2 and #3, respectively. in au4 mode, pohen[1], pohen[2] and pohen[3] identify the status of tributary path overhead bytes from tug3 #1, #2 and #3, respectively. each pohen signal is updated on the falling edge of pohck.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 78 pin name type pin no. function pohen[4] pohen[5] pohen[6] output d19 e20 e21 the tributary path overhead enable (pohen[6:4]) signals may be used to identify tributary path overhead bytes that are being presented on the corresponding poh stream of stm-1 #2 for the first time. each pohen signal is set high when a fresh overhead byte is available on the corresponding poh stream. pohen is set low when the tributary path overhead byte available on the corresponding poh stream has already been shifted out in a previous frame. pohen[4], pohen[5] and pohen[6] identify the status of tributary path overhead bytes from sts-1 (au3) #1, #2 and #3, respectively. in au4 mode, pohen[4], pohen[5] and pohen[6] identify the status of tributary path overhead bytes from tug3 #1, #2 and #3, respectively. each pohen signal is updated on the falling edge of pohck. pohen[7] pohen[8] pohen[9] output w23 w22 y22 the tributary path overhead enable (pohen[9:7]) signals may be used to identify tributary path overhead bytes that are being presented on the corresponding poh stream of stm-1 #3 for the first time. each pohen signal is set high when a fresh overhead byte is available on the corresponding poh stream. pohen is set low when the tributary path overhead byte available on the corresponding poh stream has already been shifted out in a previous frame. pohen[7], pohen[8] and pohen[9] identify the status of tributary path overhead bytes from sts-1 (au3) #1, #2 and #3, respectively. in au4 mode, pohen[7], pohen[8] and pohen[9] identify the status of tributary path overhead bytes from tug3 #1, #2 and #3, respectively. each pohen signal is updated on the falling edge of pohck.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 79 pin name type pin no. function pohen[10] pohen[11] pohen[12] output aa9 ac9 y11 the tributary path overhead enable (pohen[12:10]) signals may be used to identify tributary path overhead bytes that are being presented on the corresponding poh stream of stm-1 #4 for the first time. each pohen signal is set high when a fresh overhead byte is available on the corresponding poh stream. pohen is set low when the tributary path overhead byte available on the corresponding poh stream has already been shifted out in a previous frame. pohen[10], pohen[11] and pohen[12] identify the status of tributary path overhead bytes from sts-1 (au3) #1, #2 and #3, respectively. in au4 mode, pohen[10], pohen[11] and pohen[12] identify the status of tributary path overhead bytes from tug3 #1, #2 and #3, respectively. each pohen signal is updated on the falling edge of pohck. rad[1] output k3 the receive alarm port #1 (rad[1]) contains the tributary path bip error count, the rdi status and the pdi status of each tributary in the stm- 1 #1. rad[1] is updated on the falling edge of pohck. rad[2] output c19 the receive alarm port #2 (rad[2]) contains the tributary path bip error count, the rdi status and the pdi status of each tributary in the stm- 1 #2. rad[2] is updated on the falling edge of pohck. rad[3] output t20 the receive alarm port #3 (rad[3]) contains the tributary path bip error count, the rdi status and the pdi status of each tributary in the stm- 1 #3. rad[3] is updated on the falling edge of pohck.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 80 pin name type pin no. function rad[4] output ac7 the receive alarm port #4 (rad[4]) contains the tributary path bip error count, the rdi status and the pdi status of each tributary in the stm- 1 #4. rad[4] is updated on the falling edge of pohck. mbeb input c6 the active low motorola bus enable (mbeb) signal configures the tupp+622 for motorola bus mode where the rdb/e signal functions as e, and the wrb/rwb signal functions as rwb. when mbeb is high, the tupp+622 is configured for intel bus mode where the rdb/e signal functions as rdb. the mbeb input has an integral pull up resistor. csb input a4 the active low chip select (csb) signal is low during tupp+622 register accesses. if csb is not required (i.e., register accesses are controlled by using the rdb/e and wrb/rwb signals only), csb must be connected to an inverted version of rstb. rdb/ input b6 the active low read enable (rdb) signal is low during tupp+622 register read accesses while in intel bus mode. the tupp+622 drives the d[7:0] bus with the contents of the addressed register while rdb and csb are low. e the active high external access (e) signal is high during tupp+622 register access while in motorola bus mode.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 81 pin name type pin no. function wrb/ input c7 the active low write strobe (wrb) signal is low during a tupp+622 register write accesses while in intel bus mode. the d[7:0] bus contents are clocked into the addressed register on the rising wrb edge while csb is low. rwb the read/write select (rwb) signal selects between tupp+622 register read and write accesses while in motorola bus mode. the tupp+622 drives the d[7:0] bus with the contents of the addressed register while csb is low and rwb and e are high. the d[7:0] bus contents are clocked into the addressed register on the falling e edge while csb and rwb are low. d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] i/o a11 b12 c12 a13 b13 c13 d13 a14 the bidirectional data bus d[7:0] is used during tupp+622 register read and write accesses.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 82 pin name type pin no. function a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] input d8 b7 c8 a7 b8 c9 b9 d10 a9 c10 b10 a10 d11 the address bus a[13:0] selects specific registers during tupp+622 register accesses. a[13]/trs c11 the test register select (trs) signal selects between normal and test mode register accesses. trs is high during test mode register accesses, and is low during normal mode register accesses. rstb input d7 the active low reset (rstb) signal provides an asynchronous tupp+622 reset. rstb is a schmitt triggered input with an integral pull up resistor. ale input a5 the address latch enable (ale) is active high and latches the address bus a[13:0] when low. when ale is high, the internal address latches are transparent. it allows the tupp+622 to interface to a multiplexed address/data bus. ale has an integral pull up resistor.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 83 pin name type pin no. function intb od output c14 the active low interrupt (intb) signal goes low when a tupp+622 interrupt source is active. intb returns high when the interrupt is acknowledged via an appropriate register access. intb is an open drain output. tck input c5 the test clock (tck) signal provides timing for test operations that can be carried out using the ieee p1149.1 test access port. tck has an integral pull up resistor. tms input c4 the test mode select (tms) signal controls the test operations that can be carried out using the ieee p1149.1 test access port. tms is sampled on the rising edge of tck. tms has an integral pull up resistor. tdi input b4 the test data input (tdi) signal carries test data into the device via the ieee p1149.1 test access port. tdi is sampled on the rising edge of tck. tdi has an integral pull up resistor. tdo tristat e a3 the test data output (tdo) signal carries test data out of the device via the ieee p1149.1 test access port. tdo is updated on the falling edge of tck. tdo is a tristate output that is always tristated except when scanning of data is in progress. trstb input d5 the active low test reset (trstb) signal provides an asynchronous test access port reset. trstb is a schmitt triggered input with an integral pull up resistor. trstb must be asserted during the power up sequence.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 84 pin name type pin no. function vddi1 vddi2 vddi3 vddi4 vddi5 vddi6 vddi7 vddi8 vddi9 vddi10 vddi11 vddi12 vddi13 vddi14 vddi15 vddi16 power g2 k2 n2 u2 ab7 ab10 ab13 ab17 u22 n22 j22 e22 b17 b14 b11 b5 the core power (vddi1 ? vddi16) pins should be connected to a well decoupled +2.5 v dc supply.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 85 pin name type pin no. function vdd[35:0] power a1 a23 aa3 aa21 ab2 ab22 ac1 ac23 b2 b22 c3 c21 d4 d6 d9 d12 d15 d18 d20 f4 f20 j4 j20 m4 m20 r4 r20 v4 v20 y4 y6 y9 y12 y15 y18 y20 the pad ring switching power (vdd[35:0]) pins should be connected to a well decoupled +3.3 v dc supply.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 86 pin name type pin no. function vss[35:0] ground a2 a6 a8 a12 a16 a18 a22 aa2 aa22 ab1 ab3 ab21 ab23 ac2 ac6 ac8 ac12 ac16 ac18 ac22 b1 b3 b21 b23 c2 c22 f1 f23 h1 h23 m1 m23 t1 t23 v1 v23 the pad ring and core power ground (vss[35:0]) pins should be connected to the common ground plane of the dc supplies connected to the vdd[35:0] and the vddi1 ? vddi16 power pins. nc1 y7 reserved. must not be connected.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 87 pin name type pin no. function nc2 y16 reserved. must not be connected. notes on pin description: 1. all tupp+622 inputs and bidirectionals present minimum capacitive loading and operate at ttl logic levels. 2. all tupp+622 digital outputs and bidirectionals have 8 ma drive capability. 3. do not exceed 100 ma of current on any pin during the power-up or power-down sequence. refer to the power sequencing description in the operations section. 4. before any input activity occurs, ensure that the device power supplies are within their nominal voltage range. 5. hold the device in the reset condition until the device power supplies are within their nominal voltage range.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 88 10 functional description the tupp+622 consists of four independent stm-1 (sts-3) tributary processors (stp) each having the equivalent functionality of a tupp-plus (pm5362) device. each stp consists of three sets of tributary payload processor (vtpp), tributary path overhead processor (rtop) and tributary trace buffer (rttb). each set of vtpp, rtop and rttb is capable of processing all the tributaries in a tug3, au3 or sts-1. four stp?s, #1, #2, #3 and #4 process the stm-1 #1, #2, #3 and #4 streams, respectively. in the stm-1 (sts-3) interface mode, the incoming stm-1 #1, #2, #3 and #4 streams are sourced from the id[7:0], id[15:8], id[23:16] and id[31:24] buses, respectively. the outgoing stm-1 #1, #2, #3 and #4 streams are provided on the od[7:0], od[15:8], od[23:16] and od[31:24] buses, respectively. in the stm-4 (sts-12) interface mode, the byte- interleaved incoming stm-1 (#1, #2, #3, #4) streams of an stm-4 are sourced from the id[7:0] bus and the outgoing stm-1 (#1, #2, #3, #4) streams are byte- interleaved and provided on the od[7:0] bus as an stm-4 stream. the incoming and outgoing interface modes may be configured independently. the incoming or outgoing byte interleaved order corresponds to the stm-4 (sts-12) order of byte transmission as shown in the diagram below. the vc (spe) columns or bytes are labeled using an stm-1 (sts-3) group and au3 (sts-1) sub-group numbering scheme. distribution of incoming stm-1 streams to the stp?s is performed by the input bus demultiplexer. consolidation of outgoing stm-1 streams from the stp?s is performed by the output bus multiplexer.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 89 figure 4 - stm-4 (sts-12) order of byte transmission 1,1 1,2 1,3 2,1 2,2 2,3 3,1 3,2 3,3 4,1 4,2 4,3 1,1 1,2 1,3 2,1 2,2 2,3 3,1 3,2 3,3 4,1 4,2 4,3 twelveth byte first byte order of transmission stm-1 #, stm-0/au3 # stm-4 (sts-12) byte interleaving to generate stm-4 (sts-12) stream (sts-3 #, sts-1 #) stm-1 (sts-3) tributary processor (stp) #1 stm-1 (sts-3) tributary processor (stp) #2 stm-1 (sts-3) tributary processor (stp) #3 stm-1 (sts-3) tributary processor (stp) #4 10.1 input bus demultiplexer in stm-4 (sts-12) interface mode, the first stage of the input bus demultiplexer captures data sampled on the id[7:0] bus and distributes this data as four stm-1 (sts-3) streams to the corresponding four stm-1 (sts-3) tributary processors (stp). in stm-1 (sts-3) interface mode, the first stage of the input bus demultiplexer is bypassed and the stm-1 (sts-3) data on the id[7:0], id[15:8], id[23:16] and id[31:24] is forwarded to the respective stp?s. the input stm-1 (sts-3) demultiplexing logic of each stp provides the second stage of the input bus demultiplexer. it distributes the sts-1 (au3) or tug3 data to the three tributary payload processors within the stp.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 90 the input bus demultiplexer also provides timing signals for the other blocks within the stp. frame alignment signals for the incoming data stream, ic1j1, itmf, ipl, itv5 and itpl are sampled, buffered and distributed to the associated tributary payload processors (vtpps). in order to have synchronous operation of the vtpps with a single clock, the incoming data and control signals may be delayed by a number of system clock cycles before distribution to the vtpps. the delay is used to align the incoming data with the outgoing data at each vtpp. the amount of delay is adjusted such that the separation of the incoming sts/au frame and the outgoing frame at each vtpp appears to be in multiples of three sclk or twelve hsclk periods. when configured for au4 mode, the input bus demultiplexer provides the necessary timing coordination between the three tributary payload processors in the stp. the single j1 byte marker input on ic1j1 is retimed and distributed to each of the three tributary payload processors in the stp. the tributary multiframe detected by vtpp #1 is distributed to the two other vtpps, as vtpp #1 is the only one receiving a valid h4 byte within the stp. 10.2 output bus multiplexer the first stage of the output bus multiplexer is formed by the output multiplexing logic of each stp. it gathers payload data from the three tributary payload processors within the stp and multiplexes this data into an stm-1 (sts-3) payload data stream. it also multiplexes signals from each tributary payload processor that mark tributary spes and tributary v5 bytes into the respective stm-1 (sts-3) signals. the extracted tributary path overhead serial signals (poh[12:1], pohfp[12:1], pohen[12:1], pohck and rad[4:1]) are buffered by this stage of the output bus multiplexer block. the output bus multiplexer also provides timing signals for other blocks within an stp. frame alignment signal for the outgoing data stream, otmf, is sampled, buffered and distributed to the tributary payload processors (vtpps), tributary path overhead processors (rtops) and tributary trace buffers (rttbs) of the stp. the output bus multiplexer contains a four frame counter that will flywheel in the absence of an active otmf input, internally generating tributary multiframe timing for the outgoing stm-1 data stream. the output bus multiplexer will internally generate j1 and spe timing for the outgoing stm-1 data stream at the sts-1 (au3) or au4 level. the transport and payload frame boundaries are reported on the corresponding oc1j1v1 and opl outputs. this timing drives the outputs of the three vtpps, rtops and rttbs within the stp.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 91 in stm-4 (sts-12) interface mode, the second stage of the output bus multiplexer gathers the stm-1 (sts-3) payload data from the four stp?s and multiplexes this data onto the od[7:0] bus. it also multiplexes the stm-1 tributary spe and tributary v5 byte indication signals from the stp?s onto the otpl[1] and otv5[1] signals, respectively. in stm-1 (sts-3) interface mode, the second stage of the output bus is bypassed and the stm-1 (sts-3) payload data from the four stp?s are provided directly to the respective od[7:0], od[15:8], od[23:16] and od[31:24] buses. similarly, the stm-1 tributary spe and tributary v5 byte indication signals from the stp?s are provided directly to the respective otpl[4:1] and otv5[4:1] signals. 10.3 tributary payload processor (vtpp) each tributary payload processor (vtpp) processes the tributaries within an sts-1, au3, or tug3. each vtpp can be configured to process any legal mix of vt1.5s, vt2s, vt3s, or vt6s that can be carried in an sts-1 or any legal mix of tu11s, tu12s, tu2s, or tu3s, that can be carried in an au3 or tug3. the number of tributaries managed by each vtpp ranges from 1 (when configured to process a single tu3) to 28 (when configured to process all vt1.5s or equivalently all tu11s). 10.3.1 clock generator the clock generator derives various clocks from the 19.44 mhz system clock and distributes them to other blocks within the tributary payload processor. the overall design is totally synchronous, with processing occurring at a 6.48 mhz rate in each tributary payload processor. 10.3.2 incoming timing generator the incoming timing generator identifies the incoming tributary being processed at any given point in time. based on the configuration of the vtpp (it can process various mixes of tributary types), the incoming timing generator extracts the sts- 1 spe, vc3, or a single tug3 from a vc4, and identifies the bytes within these envelopes that correspond to various types of overhead and those that carry specific tributaries to be processed. the h4 byte is identified for the incoming multiframe detector so that it can determine the incoming tributary multiframe boundaries. the identification of specific tributaries allows the pointer interpreter to be time-sliced across the mix of tributaries present in the incoming data
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 92 stream. the identification of the v1-v3 bytes of vts, or tus (or h1-h3 bytes in the case of tu3s) allows the pointer interpreter to function. 10.3.3 incoming multiframe detector the multiframe alignment sequence in the path overhead h4 byte is monitored for the bit patterns of 00, 01, 10, 11 in the two least significant bits. if an unexpected value is detected, the primary multiframe will be kept, and a second multiframe process will, in parallel, check for a phase shift. the primary process will enter out of multiframe state (oom). a new multiframe alignment is chosen, and oom state is exited when four consecutive correct multiframe patterns are detected. loss of multiframe (lom) is declared after residing in the oom state at the ninth h4 byte without re-alignment. in counting to nine, the out of sequence h4 byte that triggered the transition to the oom state is counted as the first. a new multiframe alignment is chosen, and lom state is exited when four consecutive correct multiframe patterns are detected. changes in multiframe alignments are detected and reported. 10.3.4 pointer interpreter the pointer interpreter is a time-sliced state machine that can process up to 28 independent tributaries. the state vector is saved in ram as directed by the incoming timing generator. the pointer interpreter processes the incoming tributary pointers such that all bytes within the tributary synchronous payload envelope can be identified and written into the unique payload first-in first-out buffer for the tributary in question. a marker that tags the v5 byte (or j1 byte in the case of a tu3) is passed through the payload buffer. the incoming timing generator directs the pointer interpreter to the correct payload buffer for the tributary being processed. the pointer interpreter processes the incoming pointers (v1/v2 or h1/h2 in tu3 mode) as specified in the references. the pointer value is used to determine the location of the tributary path overhead byte (v5 or j1 in tu3) in the incoming tug3 or sts-1 (au3) stream. the algorithm can be modeled by a finite state machine. within the pointer interpretation algorithm three states are defined (as shown in figure 5): norm_state (norm) ais_state (ais)
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 93 lop_state (lop) the transition between states will be consecutive events (indications), e.g., three consecutive ais indications to go from the norm_state to the ais_state. the kind and number of consecutive indications activating a transition is chosen such that the behaviour is stable and insensitive to low ber. the only transition on a single event is the one from the ais_state to the norm_state after receiving a ndf enabled with a valid pointer value. it should be noted that, since the algorithm only contains transitions based on consecutive indications, this implies that, for example, non-consecutively received invalid indications do not activate the transitions to the lop_state. figure 5 - pointer interpretation state diagram norm inc_ind / dec_ind 3 x eq_new_point ndf_enable lop 8 x i n v _ p o i n t 8 x n d f _ e n a b l e 3 x e q _ n e w _ p o i n t ais 3 x ais_ind 8 x inv_point 3 x a i s _ i n d n d f _ e n a b l e 3 x e q _ n e w _ p o i n t
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 94 the following events (indications) are defined norm_point : disabled ndf + ss + offset value equal to active offset ndf_enable: enabled ndf + ss + offset value in range for the configured tributary type ais_ind: h1 = 'hff, h2 = 'hff inc_ind: disabled ndf + ss + majority of i bits inverted + no majority of d bits inverted + previous ndf_enable, inc_ind or dec_ind more than 3 frames ago dec_ind: disabled ndf + ss + majority of d bits inverted + no majority of i bits inverted + previous ndf_enable, inc_ind or dec_ind more than 3 frames ago inv_point: not any of above (i.e., not norm_point, and not ndf_enable, and not ais_ind, and not inc_ind and not dec_ind) new_point: disabled_ndf + ss + offset value in range for the configured tributary type but not equal to active offset inc_req: disabled ndf + ss + majority of i bits inverted + no majority of d bits inverted dec_req: disabled ndf + ss + majority of d bits inverted + no majority of i bits inverted notes: 1. active offset is defined as the accepted current phase of the spe (vc) in the norm_state and is undefined in the other states. 2. enabled ndf is defined as the following bit patterns: 1001, 0001, 1101, 1011, 1000. 3. disabled ndf is defined as the following bit patterns: 0110, 1110, 0010, 0100, 0111.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 95 4. the remaining six ndf codes (0000, 0011, 0101, 1010, 1100, 1111) result in an inv_point indication. 5. the legal range of pointer values for the five supported tributary types are: vt1.5 : 0 .. 103 vt2 : 0 .. 139 vt3 : 0 .. 211 vt6 : 0 .. 427 tu3 : 0 .. 764 6. the requirement for previous ndf_enable, inc_ind or dec_ind be more than 3 frames ago may be optionally disabled. 7. new_point is also an inv_point. 8. the requirement for 3 consecutive ais indications may be optionally disabled. the transitions indicated in the state diagram are defined as follows: inc_ind/dec_ind: offset adjustment (increment or decrement indication) 3 x eq_new_point: three consecutive equal new_point indications ndf_enable: single ndf_enable indication 3 x ais_ind: three consecutive ais indications 8 x inv_point: eight consecutive inv_point indications 8 x ndf_enable eight consecutive ndf_enable indications notes: 1. the transitions from norm_state to norm_state do not represent state changes but imply offset changes. 2. 3 x eq_new_point takes precedence over other events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 96 3. all three offset values received in 3 x eq_new_point must be identical. 4. "consecutive event counters" are reset to zero on a change of state. the pointer interpreter block detects loss of pointer (lop) in the incoming tributaries. lop is declared on entry to the lop_state as a result of eight consecutive invalid pointers or eight consecutive ndf enabled indications. lop is removed when the same valid pointer with normal ndf is detected for three consecutive frames. incoming tributary path ais (pointer bytes set to all ones) does not cause entry into the lop state. the pointer interpreter block also detects tributary path ais in the incoming tributaries. pais is declared on entry to the ais_state after three consecutive ais indications. pais is removed when the same valid pointer with normal ndf is detected for three consecutive frames or when a valid pointer with ndf enabled is detected. the pointer interpreter may be bypassed. external logic upstream would identify tributary payload bytes and tributary payload frame boundaries via the itpl and itv5 signals, respectively. loss of pointer and tributary path ais alarm detection will be disabled. alarm conditions are conveyed by the iais input signal. 10.3.5 payload buffer the payload buffer is a bank fifo buffers. it is synchronous in operation and is based on a time-sliced ram. the three 19.44 mhz clock cycles in each 6.48 mhz period are shared between the read and write operations. the pointer interpreter writes tributary payload data and the v5 (or tu3 j1) tag into the payload buffer. a 16 byte fifo buffer is provided for each of the (up to 28) tributaries. address information is also passed through the payload buffer to allow fifo fill status to be determined by the pointer generator. 10.3.6 outgoing timing generator the outgoing timing generator identifies the outgoing tributary byte being processed. based on the configuration of the vtpp, the outgoing timing generator effectively constructs the sts-1 spe, vc3, or vc4, and identifies the bytes within these envelopes that correspond to various types of overhead and bytes that carry specific tributaries. the identification of specific tributaries allows the pointer generator to be time-sliced across the mix of tributaries to be sourced
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 97 in the outgoing data stream. the identification of the v1-v3 bytes of vts, or tus (h1-h3 bytes of tu3s) allows the pointer generator to function. the sequence of h4 bytes is generated by each tributary payload processor and inserted into the outgoing administrative units. the six most significant bits of h4 are set to logic 1. the sequence of the remaining two h4 bits is determined by the corresponding otmf input. 10.3.7 pointer generator the pointer generator block generates the tributary pointers (v1/v2 or h1/h2 in tu3 mode) as specified in the references. the pointer value is used to determine the location of the tributary path overhead byte (v5 or j1 in tu3 mode) on the outgoing stream. the algorithm can be modeled by a finite state machine. within the pointer generator algorithm, five states are defined (as shown in figure 6): norm_state (norm) ais_state (ais) ndf_state (ndf) inc_state (inc) dec_state (dec) the transition from the norm to the inc, dec, and ndf states are initiated by events in the payload buffer block. the transition to/from the ais state are controlled by the pointer interpreter block. the transitions from inc, dec, and ndf states to the norm state occur autonomously with the generation of special pointer patterns.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 98 figure 6 - pointer generation state diagram norm dec inc ndf ais e s _ u p p e r t d e c _ i n d e s _ l o w e r t i n c _ i n d norm_point pi_ais ais_ind pi_ais pi_norm n d f _ e n a b ; l e f o _ d i s c o n t p i _ a i s p i _ l o p pi_ais the following events, indicated in the state diagram (figure 6), are defined:
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 99 es_lowert: es filling is below the lower threshold + previous inc_ind,dec_ind or ndf_enable more than three frames ago. es_uppert: es filling is above the upper threshold + previous inc_ind, dec_ind or ndf_enable more than three frames ago. fo_discont: frame offset discontinuity pi_ais: pi in ais state pi_lop: pi in lop state pi_norm: pi in norm state notes 1. a frame offset discontinuity occurs if an incoming ndf enabled is received, or if an elastic store overflow/underflow occurred. 2. transition to ais state due to pi_lop event may be optionally disabled. the autonomous transitions indicated in the state diagram are defined as follows: inc_ind: transmit the pointer with ndf disabled and inverted i bits, transmit a stuff byte in the byte after h3, increment active offset. dec_ind: transmit the pointer with ndf disabled and inverted d bits, transmit a data byte in the h3 byte, decrement active offset. ndf_enable: accept new offset as active offset, transmit the pointer with ndf enabled and new offset. norm_point: transmit the pointer with ndf disabled and active offset. ais_ind: active offset is undefined, transmit an all-1's pointer and payload. notes: 1. active offset is defined as the phase of the spe (vc).
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 100 2. enabled ndf is defined as the bit pattern 1001. 3. disabled ndf is defined as the bit pattern 0110. the pointer generator is a time-sliced state machine that can process up to 28 independent tributaries. the state vector is saved in ram at the address associated with the current tributary. the pointer generator fills the outgoing tributary synchronous payload envelopes with bytes read from the associated fifo in the payload buffer for the current tributary. the pointer generator creates pointers in the v1-v3 bytes (or h1-h3 bytes in the case of tu3s) of the outgoing data stream. the marker that tags the v5 byte (or j1 byte in the case of a tu3) that is passed through the payload buffer is used to align the pointer. the outgoing timing generator directs the pointer generator to the fifo in the payload buffer that is associated with the tributary being processed. the pointer generator monitors the fill levels of the payload buffers and inserts outgoing pointer justifications as necessary to avoid fifo spillage. normally, the pointer generator has a fifo dead band of two bytes. the dead band can be collapse to one so that any incoming pointer justifications will be reflected by a corresponding outgoing justification with no attenuation. signals are output by the pointer generator that identify outgoing v5 bytes (or j1 bytes in the case of a tu3) and the tributary synchronous payload envelopes. these simplify the design of mappers downstream of the tupp+622. on a per tributary basis, tributary path ais and tributary idle (unequipped) can be inserted as controlled by microprocessor accessible registers. the idle code is selectable globally for the entire vc3 or tug3 to be all-zeros or all-ones. it is also possible to force an inverted new data flag on individual tributaries for the purpose of diagnosing downstream pointer processors. tributary path ais is automatically inserted into outgoing tributaries if the pointer interpreter detects tributary path ais on the corresponding incoming tributary. 10.4 tributary path overhead processor (rtop) each tributary path overhead processor (rtop) monitors the outgoing stream of an associated tributary payload processor (vtpp) and processes the tributaries within an sts-1, au3, or tug3. each rtop can be configured to process any legal mix of vt1.5s, vt2s, vt3s, or vt6s that can be carried in an sts-1 or any legal mix of tu11s, tu12s, tu2s, or tu3s, that can be carried in an au3 or tug3. the number of tributaries managed by each rtop ranges from 1 (when configured to process a single tu3) to 28 (when configured to process all vt1.5s or all tu11s).
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 101 the rtop provides tributary performance monitoring of incoming tributaries. bit interleaved parity of the incoming tributaries is computed and compared with the bip-2 code encoded in the v5 byte of the tributary. errors between the computed and received values are accumulated. rtop also accumulates remote error indication codes. incoming path signal label is debounced and compared with the provisioned value. path signal label unstable, path signal label mismatch and change of path signal label event are identified. 10.4.1 clock generator the clock generator derives various clocks from the 19.44 mhz system clock and distributes them to other blocks within the tributary path overhead processor. the overall design is totally synchronous, with processing occurring at a 6.48 mhz rate in each tributary path overhead processor. 10.4.2 timing generator the timing generator identifies the incoming tributary being processed at any given point in time. based on the configuration of the rtop (it can process various mixes of tributary types), the incoming timing generator extracts the sts- 1 spe, vc3, or a single tug3 from a vc4, and identifies the bytes within these envelopes that correspond to various types of overhead and those that carry specific tributaries to be processed. the identification of specific tributaries allows the error monitor and extract blocks to be time-sliced across the mix of tributaries present in the incoming data stream. 10.4.3 error monitor the error monitor block is a time-sliced state machine. it relies on the timing generator block to identify the tributary being processed. the error monitor block contains a set of 12-bit counters that are used to accumulate tributary path bip-2 errors, and a set of 11-bit counters to accumulate remote error indications (rei). the contents of the counters may be transferred to a holding ram, and the counters reset under microprocessor control. tributary path bip-2 errors are detected by comparing the tributary path bip-2 bits in the v5 byte extracted from the current multiframe, to the bip-2 value computed for the previous multiframe. bip-2 errors may be accumulated on a block or nibble basis as controlled by software configurable registers. remote
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 102 error indications (reis) are detected by extracting the rei bit from the tributary path overhead byte (v5). tributary path remote defect indication (rdi) and remote failure indication (rfi) are detected by extracting bit 8 and bit 4 respectively of the tributary path overhead byte (v5). the rdi is recognized when bit 8 of the v5 byte is set high for five or ten consecutive multiframes while rfi is recognized when bit 4 of v5 is set high for five or ten consecutive multiframes. in tu3 mode, rdi is recognized when bit 5 of the g1 byte is set high for five or ten consecutive frames. bit 5 of the g1 byte is similarly processed for the status of the auxiliary rdi state. the rdi and rfi bits, and similarly bits 4 and 5 of a tu3 stream, may be treated as a two-bit code word. a code change is only recognized when the code is unchanged for five or ten frames. the tributary path signal label (psl) found in the tributary path overhead byte (v5) is processed. (c2 in tu3 mode). an incoming psl is accepted when it is received unchanged for five consecutive multiframes. the accepted psl is compared with the associated provisioned value. the psl match/mismatch state is determined by the following: table 1 - path signal label mismatch state expected psl accepted psl pslm state uneq state 000 000 match inactive 000 001 mismatch inactive 000 pdi code mismatch inactive 000 xxx 000, 001, pdi code mismatch inactive 001 000 mismatch active 001 001 match inactive 001 pdi code match inactive 001 xxx 000, 001, pdi code match inactive pdi code 000 mismatch active pdi code 001 match inactive
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 103 expected psl accepted psl pslm state uneq state pdi code pdi code match inactive pdi code xxx 000, 001, pdi code mismatch inactive xxx 000, 001, pdi code 000 mismatch active xxx 000, 001, pdi code 001 match inactive xxx 000, 001, pdi code xxx match inactive xxx 000, 001, pdi code yyy mismatch inactive each time an incoming psl differs from the one in the previous multiframe, the psl unstable counter is incremented. thus, a single bit error in the psl in a sequence of constant psl values will cause the counter to increment twice, once on the errored psl and again on the first error-free psl. the incoming psl is considered unstable when the counter reaches five. the counter is cleared when the same psl is received for five consecutive multiframes. the uneq (unequipped) state column shows the response to an accepted psl value of 000 for various expected psl settings. 10.4.4 in-band error report the in-band error report block optionally modifies the v5 byte of outgoing non- tu3 streams to report the number of detected bip errors and tributary path alarms. in-band error reporting is enabled by the iber register bits in the rtop in-band error reporting configuration registers. when in-band error reporting is enabled for non-tu3 streams, bit 3 of the v5 byte is set high when a bip-2 error is detected in the previous multiframe. bit 4 reports the rdi status. it is set high when the tributary path alarms named in the tributary remote defect indication control registers is detected and the corresponding enable register bits is also set high. similarly, bit 8 reports the auxiliary rdi status. it is set high when the tributary path alarms named in the tributary auxiliary remote defect indication control registers is detected and the
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 104 corresponding enable register bits is also set high. bits 1, 2, 5, 6 and 7 are unmodified. 10.4.5 extract the extract block uses timing information from the timing generator block to extract, serialize and output the tributary path overhead bytes (v5, j2, z6, z7) of all the processed tributaries on the corresponding poh output. the corresponding pohfp output is provided to identify the most significant bit of the v5 byte of the first tributary on the poh output. all four tributary path overhead bytes are shifted out within each payload frame period. therefore, each byte is shifted out more than once. the corresponding pohen output is used to identify fresh overhead bytes. pohen is set high when the tributary path overhead byte is shifted out for the first time. pohen is set low when the overhead byte is merely repeated. the corresponding tributary path overhead clock, pohck, is nominally a 9.72 mhz clock. 10.5 tributary trace buffer (rttb) each tributary trace buffer (rttb) monitors the outgoing stream of an associated tributary payload processor (vtpp) and processes the tributaries within an sts- 1, au3, or tug3. each rttb can be configured to process any legal mix of vt1.5s, vt2s, vt3s, or vt6s that can be carried in an sts-1 or any legal mix of tu11s, tu12s, tu2s, or tu3s, that can be carried in an au3 or tug3. the number of tributaries managed by each rttb ranges from 1 (when configured to process a single tu3) to 28 (when configured to process all vt1.5s or all tu11s). the rttb extracts the tributary path trace message contained in the j2 byte (j1 byte in tu3) to a set of internal buffers. the buffers are microprocessor accessible to allow system software to examine the messages. another set of buffers is provided for system software to download the expected message. the rttb compares the received message with the provisioned message and reports on the state of match. the rttb also monitors for unstable incoming tributary path trace messages. 10.5.1 clock generator the clock generator derives various clocks from the 19.44 mhz system clock and distributes them to other blocks within the tributary trace buffer. the overall
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 105 design is totally synchronous, with processing occurring at a 6.48 mhz rate in each tributary trace buffer. 10.5.2 timing generator the timing generator identifies the incoming tributary being processed at any given point in time. based on the configuration of the rttb (it can process various mixes of tributary types), the incoming timing generator extracts the sts- 1 spe, vc3, or a single tug3 from a vc4, and identifies the bytes within these envelopes that correspond to various types of overhead and those that carry specific tributaries to be processed. the identification of specific tributaries allows the alarm monitor and extract blocks to be time-sliced across the mix of tributaries present in the incoming data stream. 10.5.3 extract the extract block is a time-sliced state machine. it uses timing information from the timing generator block to extract the tributary path trace message bytes (j2) from all the processed tributaries in the incoming stream. each tributary in the incoming stream is allocated an individual receive buffer in the buffer block. the length of the message and, consequently, the depth of the corresponding buffer are register programmable to be 16 or 64 bytes. bytes in the message may be written to the corresponding buffer in a circular fashion or optionally be synchronized to the framing pattern embedded in the message. for a 16 byte message, the first byte is identified by a logic one in the most significant bit. for a 64 byte message, the last two bytes are set to the ascii characters of carriage- return (0dh) and linefeed (0ah). 10.5.4 alarm monitor the alarm monitor block is a time-sliced state machine. it relies on the timing generator block to identify the tributary being processed. the alarm monitor block accesses an individual capture and expected buffers in the buffer block for each tributary in the incoming stream. it also monitors the received message for consistency. when the identical message is received three or five times, as controlled by the per5 register bit, the message is accepted. this accepted message is then compared with the expected message provisioned in the buffer block. if the accepted message differs from the expected message, the trail trace identifier mismatch (tim) alarm is raised. tim alarm is negated if the accepted
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 106 and expected messages match. an accepted message that contains all-zero bytes is treated specially. if the expected messages is not also all-zeros, the tim alarm is not affected upon accepting of an all-zero message. if the expected message is all-zeros, accepting an all-zeros message would negate tim. the alarm monitor block also monitors the incoming messages for stability. two algorithms are provided. in the first algorithm, each time the current incoming message differs from the previous message, the corresponding unstable counter is incremented by one. thus, a single bit error in a message of a sequence of constant messages will cause the counter to increment twice, once on the corrupted message, and again on the first error free message. a trail trace identifier unstable (tiu) alarm is raised when the counter exceeds the register programmable threshold. the counter is cleared and tiu negated when a set of identical messages is received and becomes the accepted message. in the second algorithm, when the current incoming message differs from the previous message, the corresponding counter starts incrementing once per message. a trail trace identifier unstable (tiu) alarm is raised when the counter exceeds the register programmable threshold. the counter is cleared and tiu negated when a set of identical messages is received and becomes the accepted message. 10.5.5 buffer the buffer block contains two pages of memory, one page for capturing the receive tributary path trace messages and the other for storing the expected messages. each tributary in the incoming stream is allocated a range of addresses using high order interleaving keyed on the tributary group number and the tributary number within the group. at the j2 byte (j1 byte in tu3 mode) of each tributary, the receive and expected pages are read. the data from the incoming stream, the receive page and the expected page are supplied to the alarm monitor block for determination of trace identifier mismatch (tim) and trace identifier unstable (tiu) alarms. at the end of the cycle, the incoming data is written to the receive page. the buffer block also contains an arbiter to allow access to the receive and expected pages by the microprocessor when neither the extract nor alarm monitor block requires access. 10.6 jtag test access port the jtag test access port block provides jtag support for boundary scan. the standard jtag extest, sample, bypass, idcode and stctest
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 107 instructions are supported. the tupp+622 identification code is 053630cd hexadecimal. 10.7 microprocessor interface the microprocessor interface block provides the logic required to interface the normal mode and test mode registers within the tupp+622 to a generic microprocessor bus. the normal mode registers are used during normal operation to configure and monitor the tupp+622 while the test mode registers are used to enhance the testability of the tupp+622. the register set is accessed as shown in the register memory map table below. tributary based normal mode registers in each stm-1 (sts-3) tributary processor (stp) are arranged in order of transmission; tu #1 in tug2 #1 of sts-1 #1 is the first tributary transmitted, while tu #4 in tug2 #7 of sts-1 #3 is the last. every register is documented and identified using the register number (reg #). the corresponding memory map address for every stm-1 (sts-3) tributary processor (stp #1, #2, #3, #4) is given in the table. register numbers or addresses that are not shown are not used and must be treated as reserved. table 2 - register memory map address a[13:0] reg # stp #1 stp #2 stp #3 stp #4 description 00 0000 0800 1000 1800 stp incoming configuration 01 0001 0801 1001 1801 stp outgoing configuration 02 0002 0802 1002 1802 stp input signal activity monitor #1, accumulation trigger 03 0003 0803 1003 1803 stp reset and identity 04 0004 0804 1004 1804 stp vtpp #1 configuration #1 05 0005 0805 1005 1805 stp vtpp #2 configuration #1 06 0006 0806 1006 1806 stp vtpp #3 configuration #1 07 0007 0807 1007 1807 stp tributary payload processor and lom interrupt enable 08 0008 0808 1008 1808 stp tributary payload processor interrupt and lom status
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 108 address a[13:0] reg # stp #1 stp #2 stp #3 stp #4 description 09 0009 0809 1009 1809 stp parity error and lom interrupt 0a 000a 080a 100a 180a stp rtop and rttb interrupt enable 0b 000b 080b 100b 180b stp rtop and rttb interrupt status 0c 000c 080c 100c 180c stp rtop #1 and rttb #1 configuration 0d 000d 080d 100d 180d stp rtop #2 and rttb #2 configuration 0e 000e 080e 100e 180e stp rtop #3 and rttb #3 configuration 10 0010 0810 1010 1810 stp tributary alarm ais control 11 0011 0811 1011 1811 stp tributary remote defect indication control 12 0012 0812 1012 1812 stp tributary auxiliary remote defect indication control 13 0013 0813 1013 1813 stp tributary path defect indication control 14 0014 0814 1014 1814 stp input signal activity monitor #2 15 0015 0815 1015 1815 stp outgoing pointer lsb 16 0016 0816 1016 1816 stp outgoing pointer msb 17 0017 0817 1017 1817 stp vtpp #1 configuration #2 18 0018 0818 1018 1818 stp vtpp #2 configuration #2 19 0019 0819 1019 1819 stp vtpp #3 configuration #2 20 0020 0820 1020 1820 vtpp #1, tu3 or tu #1 in tug2 #1, configuration and status 21 0021 0821 1021 1821 vtpp #1, tu #1 in tug2 #2, configuration and status 22 0022 0822 1022 1822 vtpp #1, tu #1 in tug2 #3, configuration and status 23 0023 0823 1023 1823 vtpp #1, tu #1 in tug2 #4, configuration and status 24 0024 0824 1024 1824 vtpp #1, tu #1 in tug2 #5, configuration and status 25 0025 0825 1025 1825 vtpp #1, tu #1 in tug2 #6, configuration and status 26 0026 0826 1026 1826 vtpp #1, tu #1 in tug2 #7, configuration and status
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 109 address a[13:0] reg # stp #1 stp #2 stp #3 stp #4 description 27 0027 0827 1027 1827 vtpp #1, tu3 or tu #1 in tug2 #1 to tug2 #7, lop interrupt 28- 2e 0028- 002e 0828- 082e 1028- 102e 1828- 182e vtpp #1, tu #2 in tug2 #1 to tug2 #7, configuration and status 2f 002f 082f 102f 182f vtpp #1, tu #2 in tug2 #1 to tug2 #7, lop interrupt 30- 36 0030- 0036 0830- 0836 1030- 1036 1830- 1836 vtpp #1, tu #3 in tug2 #1 to tug2 #7, configuration and status 37 0037 0837 1037 1837 vtpp #1, tu #3 in tug2 #1 to tug2 #7, lop interrupt 38- 3e 0038- 003e 0838- 083e 1038- 103e 1838- 183e vtpp #1, tu #4 in tug2 #1 to tug2 #7, configuration and status 3f 003f 083f 103f 183f vtpp #1, tu #4 in tug2 #1 to tug2 #7, lop interrupt 40- 5f 0040- 005f 0840- 085f 1040- 105f 1840- 185f vtpp #2 configuration and status, and lop interrupt registers 60- 7f 0060- 007f 0860- 087f 1060- 107f 1860- 187f vtpp #3 configuration and status, and lop interrupt registers a0 00a0 08a0 10a0 18a0 vtpp #1, tu3, or tu #1 in tug2 #1, alarm status a1 00a1 08a1 10a1 18a1 vtpp #1, tu #1 in tug2 #2, alarm status a2 00a2 08a2 10a2 18a2 vtpp #1, tu #1 in tug2 #3, alarm status a3 00a3 08a3 10a3 18a3 vtpp #1, tu #1 in tug2 #4, alarm status a4 00a4 08a4 10a4 18a4 vtpp #1, tu #1 in tug2 #5, alarm status a5 00a5 08a5 10a5 18a5 vtpp #1, tu #1 in tug2 #6, alarm status a6 00a6 08a6 10a6 18a6 vtpp #1, tu #1 in tug2 #7, alarm status a7 00a7 08a7 10a7 18a7 vtpp #1, tu3 or tu #1 in tug2 #1 to tug2 #7, ais interrupt a8- ae 00a8- 00ae 08a8- 08ae 10a8- 10ae 18a8- 18ae vtpp #1, tu #2 in tug2 #1 to tug2 #7, alarm status
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 110 address a[13:0] reg # stp #1 stp #2 stp #3 stp #4 description af 00af 08af 10af 18af vtpp #1, tu #2 in tug2 #1 to tug2 #7, ais interrupt b0- b6 00b0- 00b6 08b0- 08b6 10b0- 10b6 18b0- 18b6 vtpp #1, tu #3 in tug2 #1 to tug2 #7, alarm status b7 00b7 08b7 10b7 18b7 vtpp #1, tu #3 in tug2 #1 to tug2 #7, ais interrupt b8- be 00b8- 00be 08b8- 08be 10b8- 10be 18b8- 18be vtpp #1, tu #4 in tug2 #1 to tug2 #7, alarm status bf 00bf 08bf 10bf 18bf vtpp #1, tu #4 in tug2 #1 to tug2 #7, ais interrupt c0- df 00c0- 00df 08c0- 08df 10c0- 10df 18c0- 18df vtpp #2 alarm status, and ais interrupt registers e0- ff 00e0- 00ff 08e0- 08ff 10e0- 10ff 18e0- 18ff vtpp #3 alarm status, and ais interrupt registers 100 0100 0900 1100 1900 rtop #1, tu3 or tu #1 in tug2 #1, configuration 101 0101 0901 1101 1901 rtop #1, tu3 or tu #1 in tug2 #1, config. and alarm status 102 0102 0902 1102 1902 rtop #1, tu3 or tu #1 in tug2 #1, expected path signal label 103 0103 0903 1103 1903 rtop #1, tu3 or tu #1 in tug2 #1, accepted path signal label 104 0104 0904 1104 1904 rtop #1, tu3 or tu #1 in tug2 #1, bip count lsb 105 0105 0905 1105 1905 rtop #1, tu3 or tu #1 in tug2 #1, bip count msb 106 0106 0906 1106 1906 rtop #1, tu3 or tu #1 in tug2 #1, rei count lsb 107 0107 0907 1107 1907 rtop #1, tu3 or tu #1 in tug2 #1, rei count msb 108- 10f 0108- 010f 0908- 090f 1108- 110f 1908- 190f rtop #1, tu #1 in tug2 #2, configuration and status registers 110- 117 0110- 0117 0910- 0917 1110- 1117 1910- 1917 rtop #1, tu #1 in tug2 #3, configuration and status registers
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 111 address a[13:0] reg # stp #1 stp #2 stp #3 stp #4 description 118- 11f 0118- 011f 0918- 091f 1118- 111f 1918- 191f rtop #1, tu #1 in tug2 #4, configuration and status registers 120- 127 0120- 0127 0920- 0927 1120- 1127 1920- 1927 rtop #1, tu #1 in tug2 #5, configuration and status registers 128- 12f 0128- 012f 0928- 092f 1128- 112f 1928- 192f rtop #1, tu #1 in tug2 #6, configuration and status registers 130- 137 0130- 0137 0930- 0937 1130- 1137 1930- 1937 rtop #1, tu #1 in tug2 #7, configuration and status registers 138 0138 0938 1138 1938 rtop #1, tu3 or tu #1 in tug2 #1 to tug2 #7, copsl interrupt 139 0139 0939 1139 1939 rtop #1, tu3 or tu #1 in tug2 #1 to tug2 #7, pslm interrupt 13a 013a 093a 113a 193a rtop #1, tu3 or tu #1 in tug2 #1 to tug2 #7, pslu interrupt 13b 013b 093b 113b 193b rtop #1, tu3 or tu #1 in tug2 #1 to tug2 #7, rdi interrupt 13c 013c 093c 113c 193c rtop #1, tu3 or tu #1 in tug2 #1 to tug2 #7, rfi interrupt 13d 013d 093d 113d 193d rtop #1, tu #1 in band error reporting configuration 13e 013e 093e 113e 193e rtop #1, tu #1 controllable output configuration 140- 147 0140- 0147 0940- 0947 1140- 1147 1940- 1947 rtop #1, tu #2 in tug2 #1, configuration and status registers 148- 14f 0148- 014f 0948- 094f 1148- 114f 1948- 194f rtop #1, tu #2 in tug2 #2, configuration and status registers 150- 157 0150- 0157 0950- 0957 1150- 1157 1950- 1957 rtop #1, tu #2 in tug2 #3, configuration and status registers 158- 15f 0158- 015f 0958- 095f 1158- 115f 1958- 195f rtop #1, tu #2 in tug2 #4, configuration and status registers
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 112 address a[13:0] reg # stp #1 stp #2 stp #3 stp #4 description 160- 167 0160- 0167 0960- 0967 1160- 1167 1960- 1967 rtop #1, tu #2 in tug2 #5, configuration and status registers 168- 16f 0168- 016f 0968- 096f 1168- 116f 1968- 196f rtop #1, tu #2 in tug2 #6, configuration and status registers 170- 177 0170- 0177 0970- 0977 1170- 1177 1970- 1977 rtop #1, tu #2 in tug2 #7, configuration and status registers 178 0178 0978 1178 1978 rtop #1, tu #2 in tug2 #1 to tug2 #7, copsl interrupt 179 0179 0979 1179 1979 rtop #1, tu #2 in tug2 #1 to tug2 #7, pslm interrupt 17a 017a 097a 117a 197a rtop #1, tu #2 in tug2 #1 to tug2 #7, pslu interrupt 17b 017b 097b 117b 197b rtop #1, tu #2 in tug2 #1 to tug2 #7, rdi interrupt 17c 017c 097c 117c 197c rtop #1, tu #2 in tug2 #1 to tug2 #7, rfi interrupt 17d 017d 097d 117d 197d rtop #1, tu #2 in band error reporting configuration 17e 017e 097e 117e 197e rtop #1, tu #2 configurable output control 180- 187 0180- 0187 0980- 0987 1180- 1187 1980- 1987 rtop #1, tu #3 in tug2 #1, configuration and status registers 188- 18f 0188- 018f 0988- 098f 1188- 118f 1988- 198f rtop #1, tu #3 in tug2 #2, configuration and status registers 190- 197 0190- 0197 0990- 0997 1190- 1197 1990- 1997 rtop #1, tu #3 in tug2 #3, configuration and status registers 198- 19f 0198- 019f 0998- 099f 1198- 119f 1998- 199f rtop #1, tu #3 in tug2 #4, configuration and status registers 1a0- 1a7 01a0- 01a7 09a0- 09a7 11a0- 11a7 19a0- 19a7 rtop #1, tu #3 in tug2 #5, configuration and status registers
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 113 address a[13:0] reg # stp #1 stp #2 stp #3 stp #4 description 1a8- 1af 01a8- 01af 09a8- 09af 11a8- 11af 19a8- 19af rtop #1, tu #3 in tug2 #6, configuration and status registers 1b0- 1b7 01b0- 01b7 09b0- 09b7 11b0- 11b7 19b0- 19b7 rtop #1, tu #3 in tug2 #7, configuration and status registers 1b8 01b8 09b8 11b8 19b8 rtop #1, tu #3 in tug2 #1 to tug2 #7, copsl interrupt 1b9 01b9 09b9 11b9 19b9 rtop #1, tu #3 in tug2 #1 to tug2 #7, pslm interrupt 1ba 01ba 09ba 11ba 19ba rtop #1, tu #3 in tug2 #1 to tug2 #7, pslu interrupt 1bb 01bb 09bb 11bb 19bb rtop #1, tu #3 in tug2 #1 to tug2 #7, rdi interrupt 1bc 01bc 09bc 11bc 19bc rtop #1, tu #3 in tug2 #1 to tug2 #7, rfi interrupt 1bd 01bd 09bd 11bd 19bd rtop #1, tu #3 in band error reporting configuration 1be 01be 09be 11be 19be rtop #1, tu #3 configurable output control 1c0- 1c7 01c0- 01c7 09c0- 09c7 11c0- 11c7 19c0- 19c7 rtop #1, tu #4 in tug2 #1, configuration and status registers 1c8- 1cf 01c8- 01cf 09c8- 09cf 11c8- 11cf 19c8- 19cf rtop #1, tu #4 in tug2 #2, configuration and status registers 1d0- 1d7 01d0- 01d7 09d0- 09d7 11d0- 11d7 19d0- 19d7 rtop #1, tu #4 in tug2 #3, configuration and status registers 1d8- 1df 01d8- 01df 09d8- 09df 11d8- 11df 19d8- 19df rtop #1, tu #4 in tug2 #4, configuration and status registers 1e0- 1e7 01e0- 01e7 09e0- 09e7 11e0- 11e7 19e0- 19e7 rtop #1, tu #4 in tug2 #5, configuration and status registers 1e8- 1ef 01e8- 01ef 09e8- 09ef 11e8- 11ef 19e8- 19ef rtop #1, tu #4 in tug2 #6, configuration and status registers
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 114 address a[13:0] reg # stp #1 stp #2 stp #3 stp #4 description 1f0- 1f7 01f0- 01f7 09f0- 09f7 11f0- 11f7 19f0- 19f7 rtop #1, tu #4 in tug2 #7, configuration and status registers 1f8 01f8 09f8 11f8 19f8 rtop #1, tu #4 in tug2 #1 to tug2 #7, copsl interrupt 1f9 01f9 09f9 11f9 19f9 rtop #1, tu #4 in tug2 #1 to tug2 #7, pslm interrupt 1fa 01fa 09fa 11fa 19fa rtop #1, tu #4 in tug2 #1 to tug2 #7, pslu interrupt 1fb 01fb 09fb 11fb 19fb rtop #1, tu #4 in tug2 #1 to tug2 #7, rdi interrupt 1fc 01fc 09fc 11fc 19fc rtop #1, tu #4 in tug2 #1 to tug2 #7, rfi interrupt 1fd 01fd 09fd 11fd 19fd rtop #1, tu #4 in band error reporting configuration 1fe 01fe 09fe 11fe 19fe rtop #1, tu #4 configurable output control 1ff 01ff 09ff 11ff 19ff rtop #1 status 200- 2ff 0200- 02ff 0a00- 0aff 1200- 12ff 1a00- 1aff rtop #2 registers 300- 3ff 0300- 03ff 0b00- 0bff 1300- 13ff 1b00- 1bff rtop #3 registers 400 0400 0c00 1400 1c00 rttb #1, tu3 or tu #1 in tug2 #1 configuration and status 401 0401 0c01 1401 1c01 rttb #1, tu #1 in tug2 #2 configuration and status 402 0402 0c02 1402 1c02 rttb #1, tu #1 in tug2 #3 configuration and status 403 0403 0c03 1403 1c03 rttb #1, tu #1 in tug2 #4 configuration and status 404 0404 0c04 1404 1c04 rttb #1, tu #1 in tug2 #5 configuration and status 405 0405 0c05 1405 1c05 rttb #1, tu #1 in tug2 #6 configuration and status 406 0406 0c06 1406 1c06 rttb #1, tu #1 in tug2 #7 configuration and status
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 115 address a[13:0] reg # stp #1 stp #2 stp #3 stp #4 description 408- 40e 0408- 040e 0c08- 0c0e 1408- 140e 1c08- 1c0e rttb #1, tu #2 in tug2 #1 to tug2 #7, configuration and status 410- 416 0410- 0416 0c10- 0c16 1410- 1416 1c10- 1c16 rttb #1, tu #3 in tug2 #1 to tug2 #7, configuration and status 418- 41e 0418- 041e 0c18- 0c1e 1418- 141e 1c18- 1c1e rttb #1, tu #4 in tug2 #1 to tug2 #7, configuration and status 420 0420 0c20 1420 1c20 rttb #1, tu3 or tu #1 in tug2 #1 to tug2 #7, tim interrupt 421 0421 0c21 1421 1c21 rttb #1, tu #2 in tug2 #1 to tug2 #7, tim interrupt 422 0422 0c22 1422 1c22 rttb #1, tu #3 in tug2 #1 to tug2 #7, tim interrupt 423 0423 0c23 1423 1c23 rttb #1, tu #4 in tug2 #1 to tug2 #7, tim interrupt 424 0424 0c24 1424 1c24 rttb #1, tu3 or tu #1 in tug2 #1 to tug2 #7, tiu interrupt 425 0425 0c25 1425 1c25 rttb #1, tu #2 in tug2 #1 to tug2 #7, tiu interrupt 426 0426 0c26 1426 1c26 rttb #1, tu #3 in tug2 #1 to tug2 #7, tiu interrupt 427 0427 0c27 1427 1c27 rttb #1, tu #4 in tug2 #1 to tug2 #7, tiu interrupt 428 0428 0c28 1428 1c28 rttb #1, tiu threshold 429 0429 0c29 1429 1c29 rttb #1, indirect tributary select 42a 042a 0c2a 142a 1c2a rttb #1, indirect buffer address 42b 042b 0c2b 142b 1c2b rttb #1, indirect data 440- 47f 0440- 047f 0c40- 0c7f 1440- 147f 1c40- 1c7f rttb #2 registers
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 116 address a[13:0] reg # stp #1 stp #2 stp #3 stp #4 description 480- 4bf 0480- 04bf 0c80- 0cbf 1480- 14bf 1c80- 1cbf rttb #3 registers 2000 master test 2001- 3fff reserved for test notes on register memory map: 1. for all register accesses, csb must be low. 2. addresses that are not shown must be treated as reserved. 3. a[13] is the test resistor select (trs) and should be set to logic 0 for normal mode register access. 4. all register numbers and addresses shown are in hexadecimal.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 117 11 normal mode register description normal mode registers are used to configure and monitor the operation of the tupp+622. normal mode registers (as opposed to test mode registers) are selected when trs (a[13]) is low. notes on normal mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic 0. reading back unused bits can produce either a logic 1 or a logic 0; hence unused register bits should be masked off by software when read. 2. all configuration bits that can be written into can also be read back. this allows the processor controlling the tupp+622 to determine the programming state of the device. 3. writeable normal mode register bits are cleared to logic 0 upon reset unless otherwise noted. 4. writing into read-only normal mode register bit locations does not affect tupp+622 operation unless otherwise noted. 5. certain register bits are reserved. these bits are associated with megacell functions that are unused in this application. to ensure that the tupp+622 operates as intended, reserved register bits must only be written with the logic level as specified. writing to reserved registers should be avoided.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 118 11.1 top level configuration registers register 00h: stp incoming configuration bit type function default bit 7 r/w ipe 0 bit 6 r/w lopais 0 bit 5 r/w incipl 0 bit 4 r/w incic1j1 0 bit 3 r/w iop 0 bit 2 r/w itmfh4 0 bit 1 r/w itmfen 0 bit 0 r/w iconcat 0 this register configures the stp functionality in the tupp+622 that are related to the incoming data stream. iconcat: when set high, the iconcat bit configures the incoming section of the stp to operate in au4 mode. when the iconcat bit is set low, the incoming section operates in au3 mode (or equivalently, sts-1 mode). itmfen: when set high, the itmfen bit enables the tupp+622 to use the corresponding itmf input signal to locate tributary multiframe boundaries. the h4 bytes in the corresponding incoming data stream are ignored. when itmfen is set low, the h4 bytes are used to locate the boundaries, and the itmf signal is ignored. itmfh4: the itmfh4 bit selects the location of the itmf in the tributary multiframe. when itmfh4 is set high, itmf is pulsed high to mark the h4 byte which indicates that the next au3/4 or sts-1 frame is the first frame of the tributary
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 119 multiframe. when itmfh4 is set low, itmf marks the third byte after j1. itmfh4 is ignored if itmf is disabled by setting the itmfen bit low. iop: the iop bit controls the expected parity on the corresponding incoming parity signal idp. when iop is set high, the parity of the parity signal set, together with idp is expected to be odd. when iop is set low, the expected parity is even. membership of the parity signal set always includes id[7:0], and may include input signals ic1j1 and ipl as controlled by the incic1j1 and incipl bits, respectively. incic1j1: the incic1j1 bit controls whether the corresponding ic1j1 input signal participates in the incoming parity calculations. when incic1j1 is set high, the parity signal set includes the ic1j1 input. when incic1j1 is set low, parity is calculated without regard to the state of ic1j1. selection of odd or even parity is controlled by the iop bit. incipl: the incipl bit controls whether the corresponding ipl input signal participates in the incoming parity calculations. when incipl is set high, the parity signal set includes the ipl input. when incipl is set low, parity is calculated without regard to the state of ipl. selection of odd or even parity is controlled by the iop bit. lopais: the lopais bit is an active high ais insertion enable. when lopais is set high, ais is automatically generated on the corresponding outgoing data stream for all tributaries that are in loss of pointer state. when lopais is set low, the generation of ais on the outgoing data stream is inhibited. this bit is logically or'ed with the bit of the same name in tributary alarm ais control register. ipe: the ipe bit is an active high interrupt enable. when ipe is set high, the occurrence of a parity error on the corresponding incoming parity signal set will cause an interrupt to be asserted on the interrupt (intb) output. when ipe is set low, incoming parity errors will not cause an interrupt.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 120 register 01h: stp outgoing configuration bit type function default bit 7 r/w incopl 0 bit 6 r/w incoc1j1 0 bit 5 r/w pohpt 0 bit 4 r/w ov1en 0 bit 3 r/w oop 0 bit 2 r/w otmfh4 0 bit 1 r/w reserved 0 bit 0 r/w oconcat 0 this register configures the stp functionality in the tupp+622 that are related to the outgoing data stream. oconcat: when set high, the oconcat bit configures the outgoing section of the stp to operate in au4 mode. when the oconcat bit is set low, the outgoing section operates in au3 mode (or equivalently, sts-1 mode). reserved: the reserved bit must be set low for correct operation of the tupp+622. otmfh4: the otmfh4 bit selects the location of the corresponding otmf in the tributary multiframe. when otmfh4 is set high, otmf is pulsed high to mark the h4 byte which indicates that the next au3/4 or sts-1 frame is the first frame of the tributary multiframe. when otmfh4 is set low, otmf marks the third byte after j1. oop: the oop bit controls the parity placed on the corresponding outgoing parity signal odp. when oop is set low, the parity of outgoing data stream od[7:0], together with odp is even. when oop is set high, the parity is odd.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 121 ov1en: the ov1en bit controls the identification of the third byte after j1 in the v1 frame. when ov1en is set low, the corresponding oc1j1v1 output only indicates the c1 and j1 bytes. the third byte after j1 is not indicated. when ov1en is set high, the corresponding oc1j1v1 output indicates the c1, j1 and the third byte after j1. pohpt: the pohpt bit controls the data of the path overhead column on the corresponding outgoing sts-1 (au3, au4) streams. when pohpt is set low, the outgoing poh columns (except the h4 byte) are set to all-zeros. when pohpt is set high, the poh column (except the h4 byte) of the corresponding incoming stream is transferred to the outgoing stream. a two frame elastic store buffer is provided to absorb phase variations between the incoming and outgoing frames. incoc1j1: the incoc1j1 bit controls whether the corresponding oc1j1v1 output signal participates in the outgoing parity calculations. when incoc1j1 is set high, the parity signal set includes the oc1j1v1 output. when incoc1j1 is set low, parity is calculated without regard to the state of oc1j1v1. selection of odd or even parity is controlled by the oop bit. incopl: the incopl bit controls whether the corresponding opl output signal participates in the outgoing parity calculations. when incopl is set high, the parity signal set includes the opl output. when incopl is set low, parity is calculated without regard to the state of opl. selection of odd or even parity is controlled by the oop bit.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 122 register 02h: stp input signal activity monitor #1, accumulation trigger bit type function default bit 7 r otmfa x bit 6 unused x bit 5 r gsclk_fpa x bit 4 r ida x bit 3 r itmfa x bit 2 r ipla x bit 1 r ic1j1a x bit 0 r sclka x this register, along with the stp input signal activity monitor #2, provides activity monitoring on major tupp+622 inputs. when a monitored input makes a low to high transition, the corresponding register bit is set high. the bit will remain high until this register is read, at which point, all the bits in this register are cleared. a lack of transitions is indicated by the corresponding register bit reading low. this register should be read periodically to detect for stuck at conditions. writing to this register delimits the accumulation intervals in the rtop accumulation registers. counts accumulated in those registers are transferred to holding registers where they can be read. the counters themselves are then cleared to begin accumulating events for a new accumulation interval. to prevent loss of data, accumulation intervals must be 0.5 second or shorter. the bits in this register are not affected by write accesses. sclka: the sclk active (sclka) bit monitors for low to high transitions on the sclk input. sclka is set high on a rising edge of sclk, and is set low when this register is read.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 123 ic1j1a: the ic1j1 active (ic1j1a) bit monitors for low to high transitions on the corresponding ic1j1 input. ic1j1a is set high on a rising edge of ic1j1, and is set low when this register is read. ipla: the ipl active (ipla) bit monitors for low to high transitions on the corresponding ipl input. ipla is set high on a rising edge of ipl, and is set low when this register is read. itmfa: the itmf active (itmfa) bit monitors for low to high transitions on the corresponding itmf input. itmfa is set high on a rising edge of itmf, and is set low when this register is read. ida: the id bus active (ida) bit monitors for low to high transitions on the corresponding input data bus. ida is set high when rising edges have been observed on all the signals on the input data bus, and is set low when this register is read. gsclk_fpa: the gsclk_fp active (gsclk_fpa) bit monitors for low to high transitions on the corresponding gsclk_fp input. gsclk_fpa is set high on a rising edge of gsclk_fp, and is set low when this register is read. otmfa: the otmf active (otmfa) bit monitors for low to high transitions on the corresponding otmf input. otmfa is set high on a rising edge of otmf, and is set low when this register is read.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 124 register 03h: stp reset and identity bit type function default bit 7 r/w reset 0 bit 6 r type 1 bit 5 r id[5] 0 bit 4 r id[4] 0 bit 3 r id[3] 0 bit 2 r id[2] 0 bit 1 r id[1] 0 bit 0 r id[0] 1 this register allows the revision of the tupp+622 to be read by software permitting graceful migration to support for newer, feature enhanced versions of the tupp+622, should revision of the tupp+622 occur. it also provides software reset capability. id[5:0]: the id bits can be read to provide a binary tupp+622 revision number. type: this legacy type bit is set high in the tupp+622 to indicate the tupp-plus (like) functionality provided by each stp. this bit is implemented in the tupp+622 to maintain software backward compatibility with the tupp-plus (pm5362) device. reset: the reset bit allows the associated stp in the tupp+622 to be reset under software control. if the reset bit is a logic 1, the stp is held in reset. this bit is not self-clearing. therefore, a logic 0 must be written to bring the stp out of reset. holding the stp in a reset state places it into a low power, stand-by mode. a hardware reset clears the reset bit, thus negating the software reset. otherwise the effect of a software reset is equivalent to that of a hardware reset for the stp.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 125 register 04h: stp vtpp #1 configuration #1 bit type function default bit 7 r/w tugen 0 bit 6 r/w sos 0 bit 5 r/w monis 0 bit 4 r/w reserved 0 bit 3 r/w nofilt 0 bit 2 r/w tu3 0 bit 1 r/w itug3 0 bit 0 r/w otug3 0 this register is used to enable the processing of sts-1 #1 (tug3 #1) and configure the major operational modes of vtpp #1. otug3: when set high, the otug3 bit configures the tributary payload processor to process a tu3 or tug2s that have been mapped into a tug3 in the outgoing data stream. when set low, the tributary payload processor defaults to processing tug2s that have been mapped into a vc3, or equivalently, vt groups that have been mapped into an sts-1. itug3: when set high, the itug3 bit configures the tributary payload processor to process a tu3 or tug2s that have been mapped into a tug3 in the incoming data stream. when set low, the tributary payload processor defaults to processing tug2s that have been mapped into a vc3, or equivalently, vt groups that have been mapped into an sts-1. tu3: when set high, the tu3 bit configures the tributary payload processor to process a single tu3 that has been mapped into a tug3. the programming of the itug3 and otug3 bits are ignored. both the incoming and outgoing streams are affected simultaneously by the tu3 bit. in tu3 mode, registers
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 126 20h and 27h reflect tu3 status and configuration, all other registers relating to tug2s and the tributaries within tug2s are disabled; data written is ignored, data read is invalid. out of tu3 mode, register 20h reflects status and configuration of tug2 #1, tu #1 and register 27h reflect lop interrupt status of tu #1 in all seven tug #2s. when changing the value of the tu3 bit, tributary processing must be disabled (tugen must have a value of logic zero). nofilt: the nofilt bit controls the processing of incoming tributary pointers. when a logic 0 is written to this location, illegal variations from normal tributary pointer value (i.e. changes which do not correspond to pointer justification events, and are not accompanied by a new data flag) are ignored unless a consistent new value is received three times consecutively. when a logic 1 is written to this location, variations take effect immediately and are passed through the payload buffer unfiltered. reserved: the reserved bit must be set low for correct operation of the tupp+622. monis: the monis bit controls the source of pointer justification interrupts. when monis is set high, the incoming stream is monitored for tributary pointer justification events. when monis is set low, the outgoing stream is monitored for pointer justification events. interrupts can be optionally generated upon a pointer justification event in the monitored stream. sos: the sos bit controls the spacing between consecutive pointer justification events on the incoming stream. when sos is set high, the definition of inc_ind and dec_ind indications includes the requirement that active offset changes have occurred at least three frames ago. when sos is set low, pointer justification indications in the incoming stream are followed without regard to the proximity of previous active offset change. this bit does not apply to set new pointer events (i.e. ndf?s).
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 127 tugen: when set high, the tugen bit enables the processing of tributaries in sts-1 #1 (tug3 #1). when tugen is low, vtpp #1, rtop #1 and rttb #1 are held in a low power, reset state. the data in sts-1 #1 (tug3 #1) is re- transmitted unchanged on the outgoing data stream. the amount of delay from the incoming to the outgoing data stream is a function of the internal data-path pipeline delay and gsclk_fp input. see the bypass functional timing diagram for details. when tugen is set low, all vttp #1, rtop #1, and rttb #1 registers are reset to their default states. before the tugen bit is set high, it is essential to first set the noic1j1plbyp bit in the stp vtpp #1 configuration #2 register high. this will ensure that the re-transmission of the corresponding input telecom bus signals, ic1j1 and ipl, to the output telecom bus is terminated gracefully.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 128 register 05h: stp vtpp #2 configuration #1 bit type function default bit 7 r/w tugen 0 bit 6 r/w sos 0 bit 5 r/w monis 0 bit 4 r/w reserved 0 bit 3 r/w nofilt 0 bit 2 r/w tu3 0 bit 1 r/w itug3 0 bit 0 r/w otug3 0 this register is used to enable the processing of sts-1 #2 (tug3 #2) and configure the major operational modes of vtpp #2. otug3: when set high, the otug3 bit configures the tributary payload processor to process a tu3 or tug2s that have been mapped into a tug3 in the outgoing data stream. when set low, the tributary payload processor defaults to processing tug2s that have been mapped into a vc3, or equivalently, vt groups that have been mapped into an sts-1. itug3: when set high, the itug3 bit configures the tributary payload processor to process a tu3 or tug2s that have been mapped into a tug3 in the incoming data stream. when set low, the tributary payload processor defaults to processing tug2s that have been mapped into a vc3, or equivalently, vt groups that have been mapped into an sts-1. tu3: when set high, the tu3 bit configures the tributary payload processor to process a single tu3 that has been mapped into a tug3. the programming of the itug3 and otug3 bits are ignored. both the incoming and outgoing streams are affected simultaneously by the tu3 bit. in tu3 mode, registers
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 129 40h and 47h reflect tu3 status and configuration, all other registers relating to tug2s and the tributaries within tug2s are disabled; data written is ignored, and read data is invalid. out of tu3 mode, register 40h reflects status and configuration of tug2 #1, tu #1 and register 47h reflect lop interrupt status of tu #1 in all seven tug #2s. when changing the value of the tu3 bit, tributary processing must be disabled (tugen must have a value of logic zero). nofilt: the nofilt bit controls the processing of incoming tributary pointers. when a logic 0 is written to this location, illegal variations from normal tributary pointer value (i.e. changes which do not correspond to pointer justification events, and are not accompanied by a new data flag) are ignored unless a consistent new value is received three times consecutively. when a logic 1 is written to this location, variations take effect immediately and are passed through the payload buffer unfiltered. reserved: the reserved bit must be set low for correct operation of the tupp+622. monis: the monis bit controls the source of pointer justification interrupts. when monis is set high, the incoming stream is monitored for tributary pointer justification events. when monis is set low, the outgoing stream is monitored for pointer justification events. interrupts can be optionally generated upon a pointer justification event in the monitored stream. sos: the sos bit controls the spacing between consecutive pointer justification events on the incoming stream. when sos is set high, the definition of inc_ind and dec_ind indications includes the requirement that active offset changes have occurred at least three frames ago. when sos is set low, pointer justification indications in the incoming stream are followed without regard to the proximity of previous active offset change. this bit does not apply to set new pointer events (i.e. ndf?s).
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 130 tugen: when set high, the tugen bit enables the processing of tributaries in sts-1 #2 (tug3 #2). when tugen is low, vtpp #2, rtop #2 and rttb #2 are held in a low power, reset state. the data in sts-1 #2 (tug3 #2) is re- transmitted unchanged on the outgoing data stream. the amount of delay from the incoming to the outgoing data stream is a function of the internal data-path pipeline delay and gsclk_fp input. see the bypass functional timing diagram for details. when tugen is set low, all vttp #2, rtop #2, and rttb #2 registers are reset to their default states. before the tugen bit is set high, it is essential to first set the noic1j1plbyp bit in the stp vtpp #2 configuration #2 register high. this will ensure that the re-transmission of the corresponding input telecom bus signals, ic1j1 and ipl, to the output telecom bus is terminated gracefully.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 131 register 06h: stp vtpp #3 configuration #1 bit type function default bit 7 r/w tugen 0 bit 6 r/w sos 0 bit 5 r/w monis 0 bit 4 r/w reserved 0 bit 3 r/w nofilt 0 bit 2 r/w tu3 0 bit 1 r/w itug3 0 bit 0 r/w otug3 0 this register is used to enable the processing of sts-1 #3 (tug3 #3) and configure the major operational modes of vtpp #1. otug3: when set high, the otug3 bit configures the tributary payload processor to process a tu3 or tug2s that have been mapped into a tug3 in the outgoing data stream. when set low, the tributary payload processor defaults to processing tug2s that have been mapped into a vc3, or equivalently, vt groups that have been mapped into an sts-1. itug3: when set high, the itug3 bit configures the tributary payload processor to process a tu3 or tug2s that have been mapped into a tug3 in the incoming data stream. when set low, the tributary payload processor defaults to processing tug2s that have been mapped into a vc3, or equivalently, vt groups that have been mapped into an sts-1. tu3: when set high, the tu3 bit configures the tributary payload processor to process a single tu3 that has been mapped into a tug3. the programming of the itug3 and otug3 bits are ignored. both the incoming and outgoing streams are affected simultaneously by the tu3 bit. in tu3 mode, registers
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 132 60h and 67h reflect tu3 status and configuration, all other registers relating to tug2s and the tributaries within tug2s are disabled; data written is ignored and read data is invalid. out of tu3 mode, register 60h reflects status and configuration of tug2 #1, tu #1 and register 67h reflect lop interrupt status of tu #1 in all seven tug #2s. when changing the value of the tu3 bit, tributary processing must be disabled (tugen must have a value of logic zero). nofilt: the nofilt bit controls the processing of incoming tributary pointers. when a logic 0 is written to this location, illegal variations from normal tributary pointer value (i.e. changes which do not correspond to pointer justification events, and are not accompanied by a new data flag) are ignored unless a consistent new value is received three times consecutively. when a logic 1 is written to this location, variations take effect immediately and are passed through the payload buffer unfiltered. reserved: the reserved bit must be set low for correct operation of the tupp+622. monis: the monis bit controls the source of pointer justification interrupts. when monis is set high, the incoming stream is monitored for tributary pointer justification events. when monis is set low, the outgoing stream is monitored for pointer justification events. interrupts can be optionally generated upon a pointer justification event in the monitored stream. sos: the sos bit controls the spacing between consecutive pointer justification events on the incoming stream. when sos is set high, the definition of inc_ind and dec_ind indications includes the requirement that active offset changes have occurred at least three frames ago. when sos is set low, pointer justification indications in the incoming stream are followed without regard to the proximity of previous active offset change. this bit does not apply to set new pointer events (i.e. ndf?s).
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 133 tugen: when set high, the tugen bit enables the processing of tributaries in sts-1 #3 (tug3 #3). when tugen is low, vtpp #3, rtop #3 and rttb #3 are held in a low power, reset state. the data in sts-1 #3 (tug3 #3) is re- transmitted unchanged on the outgoing data stream. the amount of delay from the incoming to the outgoing data stream is a function of the internal data-path pipeline delay and gsclk_fp input. see the bypass functional timing diagram for details. when tugen is set low, all vttp #3, rtop #3, and rttb #3 registers are reset to their default states. before the tugen bit is set high, it is essential to first set the noic1j1plbyp bit in the stp vtpp #3 configuration #2 register high. this will ensure that the re-transmission of the corresponding input telecom bus signals, ic1j1 and ipl, to the output telecom bus is terminated gracefully.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 134 register 07h: stp tributary payload processor and lom interrupt enable bit type function default bit 7 unused x bit 6 unused x bit 5 r/w lom3e 0 bit 4 r/w lom2e 0 bit 3 r/w lom1e 0 bit 2 r/w vtpp3e 0 bit 1 r/w vtpp2e 0 bit 0 r/w vtpp1e 0 this register provides interrupt enable of the three h4 byte framers and of the three tributary payload processors in the stp. vtpp1e: vtpp1e is the interrupt enable bit for tributary payload processor #1 in the stp. interrupts enabled at tributary processor #1 but masked by vtpp1e will still be reported by the vtpp1i bit, although the interrupt output will not be activated. interrupts disabled at tributary payload processor #1 will not be reported by the vtpp1i bit. vtpp2e: vtpp2e is the interrupt enable bit for tributary processor #2 in the stp. interrupts enabled at tributary payload processor #2 but masked by vtpp2e will still be reported by the vtpp2i bit, although the interrupt output will not be activated. interrupts disabled at tributary payload processor #2 will not be reported by the vtpp2i bit. vtpp3e: vtpp3e is the interrupt enable bit for tributary payload processor #3 in the stp. interrupts enabled at tributary processor #3 but masked by vtpp3e will still be reported by the vtpp3i bit, although the interrupt output will not be
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 135 activated. interrupts disabled at tributary payload processor #3 will not be reported by the vtpp3i bit. lom1e: the lom1e bit is an interrupt enable bit for the h4 framer out of frame interrupt in tributary payload processor #1. when lom1e is set high, a change in the framer out of frame status will cause an interrupt to be generated on the intb output. interrupts are masked when lome is set low. lom2e: the lom2e bit is an interrupt enable bit for the h4 framer out of frame interrupt in tributary payload processor #2. when lom2e is set high, a change in the framer out of frame status will cause an interrupt to be generated on the intb output. interrupts are masked when lome is set low. when iconcat is set to logic 1 this interrupt enable bit should be set to logic 0. in the au4 mode the multiframe alignment is determined by the h4 byte framer in tributary payload processor #1. lom3e: the lom3e bit is an interrupt enable bit for the h4 framer out of frame interrupt in tributary payload processor #3. when lom3e is set high, a change in the framer out of frame status will cause an interrupt to be generated on the intb output. interrupts are masked when lome is set low. when iconcat is set to logic 1 this interrupt enable bit should be set to logic 0. in the au4 mode the multiframe alignment is determined by the h4 byte framer in tributary payload processor #1.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 136 register 08h: stp tributary payload processor interrupt and lom status bit type function default zbit 7 unused x bit 6 unused x bit 5 r lom3v 0 bit 4 r lom2v 0 bit 3 r lom1v 0 bit 2 r vtpp3i 0 bit 1 r vtpp2i 0 bit 0 r vtpp1i 0 this register provides interrupt status of the three h4 byte framers and of the three tributary payload processors in the stp. vtpp1i: vtpp1i identifies tributary payload processor #1 as the source of a pending interrupt. it is necessary to read the various interrupt status registers in tributary payload processor #1 to determine the event causing the interrupt and to clear the interrupt. interrupts disabled at tributary payload processor #1 will not be reported by the vtpp1i bit. vtpp2i: vtpp2i identifies tributary payload processor #2 as the source of a pending interrupt. it is necessary to read the various interrupt status registers in tributary payload processor #2 to determine the event causing the interrupt and to clear the interrupt. interrupts disabled at tributary payload processor #2 will not be reported by the vtpp2i bit. vtpp3i: vtpp1i identifies tributary payload processor #3 as the source of a pending interrupt. it is necessary to read the various interrupt status registers in tributary payload processor #3 to determine the event causing the interrupt
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 137 and to clear the interrupt. interrupts disabled at tributary payload processor #3 will not be reported by the vtpp3i bit. lom1v: the lom1v bit indicates the status of the h4 byte framer in tributary payload processor #1. lom1v is set high when the h4 framer is in loss of multiframe state and is set low when it re-acquires multiframe alignment. lom2v: the lom2v bit indicates the status of the h4 byte framer in tributary payload processor #2. lom2v is set high when the h4 framer is in loss of multiframe state and is set low when it re-acquires multiframe alignment. when iconcat is set to logic 1 this status bit should be ignored since the multiframe alignment is determined by the h4 byte framer in tributary payload processor #1. lom3v: the lom3v bit indicates the status of the h4 byte framer in tributary payload processor #3. lom3v is set high when the h4 framer is in loss of multiframe state and is set low when it re-acquires multiframe alignment. when iconcat is set to logic 1 this status bit should be ignored since the multiframe alignment is determined by the h4 byte framer in tributary payload processor #1.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 138 register 09h: stp parity error and lom interrupt bit type function default bit 7 r ipi 0 bit 6 unused x bit 5 r lom3i 0 bit 4 r lom2i 0 bit 3 r lom1i 0 bit 2 r/w reserved3 1 bit 1 r/w reserved2 1 bit 0 r/w reserved1 1 this register provides interrupt status of the h4 byte framers in the three tributary payload processor and of the input parity checker in the stp. reserved[3:1]: the reserved[3:1] bits must be set high for the correct operation of the tupp+622. lom1i: the lom1i bit indicates a change of status in the h4 byte framer. interrupts are generated when the h4 framer in tributary payload processor #1 enters loss of multiframe state and when it re-acquires multiframe alignment. the lom1i bit is set high on entry and exit to the loss of multiframe state and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. the lomi bit remains valid when interrupts are not enabled (lom1e set low) and may be polled to detect out of frame events. lom2i: the lom2i bit indicates a change of status in the h4 byte framer. interrupts are generated when the h4 framer in tributary payload processor #2 enters loss of multiframe state and when it re-acquires multiframe alignment. the lom2i bit is set high on entry and exit to the loss of multiframe state and is
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 139 cleared immediately following a read of this register, which also acknowledges and clears the interrupt. the lom2i bit remains valid when interrupts are not enabled (lom2e set low) and may be polled to detect out of frame events. lom3i: the lom3i bit indicates a change of status in the h4 byte framer. interrupts are generated when the h4 framer in tributary payload processor #3 enters loss of multiframe state and when it re-acquires multiframe alignment. the lom3i bit is set high on entry and exit to the loss of multiframe state and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. the lom3i bit remains valid when interrupts are not enabled (lom3e set low) and may be polled to detect out of frame events. ipi: the incoming parity error interrupt bit (ipi) is set high when a parity error is detected on the incoming parity signal set. if the ipe bit in the stp incoming configuration register is set high, the interrupt output (intb) is activated. when this register is read, ipi (and the corresponding interrupt) is cleared.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 140 register 0ah: stp rtop and rttb interrupt enable bit type function default bit 7 unused x bit 6 unused x bit 5 r/w rttb3e 0 bit 4 r/w rttb2e 0 bit 3 r/w rttb1e 0 bit 2 r/w rtop3e 0 bit 1 r/w rtop2e 0 bit 0 r/w rtop1e 0 this register provides interrupt enable of the three tributary path overhead processors and of the three tributary trace buffers in the stp. rtop1e: rtop1e is the interrupt enable bit for tributary path overhead processor #1 in the stp. interrupts enabled at tributary path overhead processor #1 but masked by rtop1e will still be reported by the rtop1i bit, although the interrupt output will not be activated. interrupts disabled at tributary path overhead processor #1 will not be reported by the rtop1i bit. rtop2e: rtop2e is the interrupt enable bit for tributary path overhead processor #2 in the stp. interrupts enabled at tributary path overhead processor #2 but masked by rtop2e will still be reported by the rtop2i bit, although the interrupt output will not be activated. interrupts disabled at tributary path overhead processor #2 will not be reported by the rtop2i bit. rtop3e: rtop3e is the interrupt enable bit for tributary path overhead processor #3 in the stp. interrupts enabled at tributary path overhead processor #3 but masked by rtop3e will still be reported by the rtop3i bit, although the
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 141 interrupt output will not be activated. interrupts disabled at tributary path overhead processor #3 will not be reported by the rtop3i bit. rttb1e: rttb1e is the interrupt enable bit for tributary trace buffer #1 in the stp. interrupts enabled at tributary trace buffer #1 but masked by rttb1e will still be reported by the rttb1i bit, although the interrupt output will not be activated. interrupts disabled at tributary trace buffer #1 will not be reported by the rttb1i bit. rttb2e: rttb2e is the interrupt enable bit for tributary trace buffer #2 in the stp. interrupts enabled at tributary trace buffer #2 but masked by rttb2e will still be reported by the rttb2i bit, although the interrupt output will not be activated. interrupts disabled at tributary trace buffer #2 will not be reported by the rttb2i bit. rttb3e: rttb3e is the interrupt enable bit for tributary trace buffer #3 in the stp. interrupts enabled at tributary trace buffer #3 but masked by rttb3e will still be reported by the rttb3i bit, although the interrupt output will not be activated. interrupts disabled at tributary trace buffer #3 will not be reported by the rttb3i bit.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 142 register 0bh: stp rtop and rttb interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 r rttb3i 0 bit 4 r rttb2i 0 bit 3 r rttb1i 0 bit 2 r rtop3i 0 bit 1 r rtop2i 0 bit 0 r rtop1i 0 this register provides interrupt status of the three tributary path overhead processor and of the three tributary trace buffers in the stp. rtop1i: rtop1i identifies tributary path overhead processor #1 as the source of a pending interrupt. it is necessary to read the various interrupt status registers in tributary path overhead processor #1 to determine the event causing the interrupt and to clear the interrupt. interrupts disabled at tributary path overhead processor #1 will not be reported by the rtop1i bit. rtop2i: rtop2i identifies tributary path overhead processor #2 as the source of a pending interrupt. it is necessary to read the various interrupt status registers in tributary path overhead processor #2 to determine the event causing the interrupt and to clear the interrupt. interrupts disabled at tributary path overhead processor #2 will not be reported by the rtop2i bit. rtop3i: rtop1i identifies tributary path overhead processor #3 as the source of a pending interrupt. it is necessary to read the various interrupt status registers in tributary path overhead processor #3 to determine the event causing the
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 143 interrupt and to clear the interrupt. interrupts disabled at tributary path overhead processor #3 will not be reported by the rtop3i bit. rttb1i: rttb1i identifies tributary trace buffer #1 as the source of a pending interrupt. it is necessary to read the various interrupt status registers in tributary trace buffer #1 to determine the event causing the interrupt and to clear the interrupt. interrupts disabled at tributary trace buffer #1 will not be reported by the rttb1i bit. rttb2i: rttb2i identifies tributary trace buffer #2 as the source of a pending interrupt. it is necessary to read the various interrupt status registers in tributary trace buffer #2 to determine the event causing the interrupt and to clear the interrupt. interrupts disabled at tributary trace buffer #2 will not be reported by the rttb2i bit. rttb3i: rttb1i identifies tributary trace buffer #3 as the source of a pending interrupt. it is necessary to read the various interrupt status registers in tributary trace buffer #3 to determine the event causing the interrupt and to clear the interrupt. interrupts disabled at tributary trace buffer #3 will not be reported by the rttb3i bit.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 144 register 0ch: stp rtop #1 and rttb #1 configuration bit type function default bit 7 r/w algo2 0 bit 6 r/w per5 0 bit 5 unused x bit 4 unused x bit 3 r/w rdi10 0 bit 2 r/w pdi[2] 0 bit 1 r/w pdi[1] 0 bit 0 r/w pdi[0] 1 this register configures the operation of rtop #1 and rttb #1 in the stp. pdi[2:0]: the pdi[2:0] bits specifies the code used to convey tributary path defect indication (pdi-v) in the v5 byte (out of tu3 mode) or the c2 byte (in tu3 mode). for tu3 payloads, the pdi[2] bit is sign extended to form the byte value used for the pdi-v detection. rdi10: the rdi10 bit controls the number of times the tributary path rdi, rfi or the extended rdi code is filtered before being accepted. when rdi10 is set high, the rdi bit, the rfi bit or the extended rdi code is filtered for ten occurrences. when rdi10 is set low, the rdi bit, the rfi bit or the extended rdi code is filtered for five occurrences. per5: the per5 bit controls the number of identical tributary path trace messages needed for the message to become accepted. when per5 is set high, a messages is accepted when it is received unchanged five times. when per5 is set low, the message is accepted after three identical repetitions.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 145 algo2: the algo2 bit controls the algorithm used to detect trail trace identifier unstable alarms. when algo2 is set high, a counter starts on the first dissimilar identifier and cleared to zero when the same identifier is received enough times to be accepted. tiu is declared when the count exceeds the programmable tiu threshold. when algo2 is set low, the counter increments on each dissimilar identifier and is cleared to zero when the same identifier is received enough times to be accepted. tiu is declared when the count exceeds the programmable tiu threshold.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 146 register 0dh: stp rtop #2 and rttb #2 configuration bit type function default bit 7 r/w algo2 0 bit 6 r/w per5 0 bit 5 unused x bit 4 unused x bit 3 r/w rdi10 0 bit 2 r/w pdi[2] 0 bit 1 r/w pdi[1] 0 bit 0 r/w pdi[0] 1 this register configures the operation of rtop #2 and rttb #2 in the stp. pdi[2:0]: the pdi[2:0] bits specifies the code used to convey tributary path defect indication (pdi-v) in the v5 byte (for non-tu3 payloads) or the c2 byte (for tu3 payloads). for tu3 payloads, the pdi[2] bit is sign extended to form the byte value used for the pdi-v detection. rdi10: the rdi10 bit controls the number of times the tributary path rdi, rfi or the extended rdi code is filtered before being accepted. when rdi10 is set high, the rdi bit, the rfi bit or the extended rdi code is filtered for ten occurrences. when rdi10 is set low, the rdi bit, the rfi bit or the extended rdi code is filtered for five occurrences. per5: the per5 bit controls the number of identical tributary path trace messages needed for the message to become accepted. when per5 is set high, a messages is accepted when it is received unchanged five times. when per5 is set low, the message is accepted after three identical repetitions.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 147 algo2: the algo2 bit controls the algorithm used to detect trail trace identifier unstable alarms. when algo2 is set high, a counter starts on the first dissimilar identifier and cleared to zero when the same identifier is received enough times to be accepted. tiu is declared when the count exceeds the programmable tiu threshold. when algo2 is set low, the counter increments on each dissimilar identifier and is cleared to zero when the same identifier is received enough times to be accepted. tiu is declared when the count exceeds the programmable tiu threshold.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 148 register 0eh: stp rtop #3 and rttb #3 configuration bit type function default bit 7 r/w algo2 0 bit 6 r/w per5 0 bit 5 unused x bit 4 unused x bit 3 r/w rdi10 0 bit 2 r/w pdi[2] 0 bit 1 r/w pdi[1] 0 bit 0 r/w pdi[0] 1 this register configures the operation of rtop #3 and rttb #3 in the stp. pdi[2:0]: the pdi[2:0] bits specifies the code used to convey tributary path defect indication (pdi-v) in the v5 byte (for non-tu3 payloads) or the c2 byte (for tu3 payloads). for tu3 payloads, the pdi[2] bit is sign extended to form the byte value used for the pdi-v detection. rdi10: the rdi10 bit controls the number of times the tributary path rdi, rfi or the extended rdi code is filtered before being accepted. when rdi10 is set high, the rdi bit, the rfi bit or the extended rdi code is filtered for ten occurrences. when rdi10 is set low, the rdi bit, the rfi bit or the extended rdi code is filtered for five occurrences. per5: the per5 bit controls the number of identical tributary path trace messages needed for the message to become accepted. when per5 is set high, a messages is accepted when it is received unchanged five times. when per5 is set low, the message is accepted after three identical repetitions.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 149 algo2: the algo2 bit controls the algorithm used to detect trail trace identifier unstable alarms. when algo2 is set high, a counter starts on the first dissimilar identifier and cleared to zero when the same identifier is received enough times to be accepted. tiu is declared when the count exceeds the programmable tiu threshold. when algo2 is set low, the counter increments on each dissimilar identifier and is cleared to zero when the same identifier is received enough times to be accepted. tiu is declared when the count exceeds the programmable tiu threshold.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 150 register 10h: stp tributary alarm ais control bit type function default bit 7 r/w lomais 0 bit 6 r/w lopais 0 bit 5 unused x bit 4 r/w uneqais 0 bit 3 r/w pslmais 0 bit 2 r/w psluais 0 bit 1 r/w timais 0 bit 0 r/w tiuais 0 this register controls the insertion of tributary path ais as a result of tributary path signal label alarms, tributary trace identifier alarms and tributary multiframe alarms. tiuais: the tiuais bit is an active high ais insertion enable. when tiuais is set high, ais is automatically generated on the outgoing data stream for all tributaries that are in trace identifier unstable state. when tiuais is set low, the generation of ais on the outgoing data stream is inhibited. the negation of ais occurs at tributary multiframe boundaries. timais: the timais bit is an active high ais insertion enable. when timais is set high, ais is automatically generated on the outgoing data stream for all tributaries that are in trace identifier mismatch state. when timais is set low, the generation of ais on the outgoing data stream is inhibited. the negation of ais occurs at tributary multiframe boundaries. psluais: the psluais bit is an active high ais insertion enable. when psluais is set high, ais is automatically generated on the outgoing data stream for all tributaries that are in path signal label unstable state. when psluais is set
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 151 low, the generation of ais on the outgoing data stream is inhibited. the negation of ais occurs at tributary multiframe boundaries. pslmais: the pslmais bit is an active high ais insertion enable. when pslmais is set high, ais is automatically generated on the outgoing data stream for all tributaries that are in path signal label mismatch state. when pslmais is set low, the generation of ais on the outgoing data stream is inhibited. the negation of ais occurs at tributary multiframe boundaries. the generation of ais is inhibited when uneq is active, regardless of the pslm state. uneqais: the uneqais bit is an active high ais insertion enable. when uneqais is set high, ais is automatically generated on the outgoing data stream for all tributaries that are unequipped. when uneqais is set low, the generation of ais on the outgoing data stream is inhibited. the negation of ais occurs at tributary multiframe boundaries. lopais: the lopais bit is an active high ais insertion enable. when lopais is set high, ais is automatically generated on the outgoing data stream for all tributaries that are in loss of pointer state. when lopais is set low, the generation of ais on the outgoing data stream is inhibited. the negation of ais occurs at tributary multiframe boundaries. this bit is logically or'ed with the bit of the same name in stp incoming configuration register. lomais: the lomais bit is an active high ais insertion enable. when lomais is set high, ais is automatically generated on the outgoing data stream for all tributaries that are in loss of tributary multiframe state. when lomais is set low, the generation of ais on the outgoing data stream is inhibited. lomais has no effect on tu3 streams.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 152 register 11h: stp tributary remote defect indication control bit type function default bit 7 r/w lomrdi 0 bit 6 r/w loprdi 0 bit 5 r/w aisrdi 0 bit 4 r/w uneqrdi 0 bit 3 r/w pslmrdi 0 bit 2 r/w pslurdi 0 bit 1 r/w timrdi 0 bit 0 r/w tiurdi 0 this register controls the insertion of tributary path rdi on the receive alarm port (rad) and optionally on the v5 byte (g1 in tu3 mode) as a result of tributary pointer alarms, tributary path signal label alarms, tributary trace identifier alarms and tributary multiframe alarms. tiurdi: the tiurdi bit is an active high rdi insertion enable. when tiurdi is set high, rdi is reported on rad and optionally in the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in trace identifier unstable state. when tiurdi is set low, reporting of rdi due to tiu is inhibited. timrdi: the timrdi bit is an active high rdi insertion enable. when timrdi is set high, rdi is reported on rad and optionally in the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in trace identifier mismatch state. when tiurdi is set low, reporting of rdi due to tim is inhibited. pslurdi: the pslurdi bit is an active high rdi insertion enable. when pslurdi is set high, rdi is reported on rad and optionally in the v5 byte (g1 byte in
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 153 tu3 mode) of the outgoing data stream for all tributaries that are in path signal label unstable state. when pslurdi is set low, reporting of rdi due to pslu is inhibited. pslmrdi: the pslmrdi bit is an active high rdi insertion enable. when pslmrdi is set high, rdi is reported on rad and optionally in the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in path signal label mismatch state. when pslmrdi is set low, reporting of rdi due to pslm is inhibited. the generation of rdi is inhibited when uneq is active, regardless of the pslm state. uneqrdi: the uneqrdi bit is an active high rdi insertion enable. when uneqrdi is set high, rdi is reported on rad and optionally in the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in unequipped state. when uneqrdi is set low, reporting of rdi due to uneq is inhibited. aisrdi: the aisrdi bit is an active high rdi insertion enable. when aisrdi is set high, rdi is reported on rad and optionally the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in incoming ais state. when aisrdi is set low, reporting of rdi due to ais is inhibited. loprdi: the loprdi bit is an active high rdi insertion enable. when loprdi is set high, rdi is reported on rad and optionally the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in loss of pointer state. when loprdi is set low, reporting of rdi due to lop is inhibited. lomrdi: the lomrdi bit is an active high rdi insertion enable. when lomrdi is set high, rdi is reported on rad and optionally in the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in loss of multiframe state. when lomrdi is set low, reporting of rdi due to lom is inhibited.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 154 register 12h: stp tributary auxiliary remote defect indication control bit type function default bit 7 r/w nolomardi 1 bit 6 r/w nolopardi 1 bit 5 r/w noaisardi 1 bit 4 r/w uneqardi 0 bit 3 r/w pslmardi 0 bit 2 r/w psluardi 0 bit 1 r/w timardi 0 bit 0 r/w tiuardi 0 this register controls the insertion of tributary path auxiliary rdi on the receive alarm port (rad) and optionally on the v5 byte (g1 in tu3 mode) as a result of tributary pointer alarms, tributary path signal label alarms, tributary trace identifier alarms and tributary multiframe alarms. tiuardi: the tiuardi bit is an active high auxiliary rdi insertion enable. when tiuardi is set high, ardi is reported on rad and optionally in the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in trace identifier unstable state. when tiurdi is set low, reporting of auxiliary rdi due to tim is inhibited. timardi: the timardi bit is an active high auxiliary rdi insertion enable. when timardi is set high, ardi is reported on rad and optionally in the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in trace identifier mismatch state. when tiuardi is set low, reporting of auxiliary rdi due to tim is inhibited. psluardi: the psluardi bit is an active high auxiliary rdi insertion enable. when psluardi is set high, ardi is reported on rad and optionally in the v5 byte
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 155 (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in path signal label unstable state. when psluardi is set low, reporting of auxiliary rdi due to pslu is inhibited. pslmardi: the pslmardi bit is an active high auxiliary rdi insertion enable. when pslmardi is set high, ardi is reported on rad and optionally in the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in path signal label mismatch state. when pslmardi is set low, reporting of auxiliary rdi due to pslm is inhibited. the generation of ardi is inhibited when uneq is active, regardless of the pslm state. uneqardi: the uneqardi bit is an active high auxiliary rdi insertion enable. when uneqardi is set high, ardi is reported on rad and optionally in the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in unequipped state. when uneqardi is set low, the reporting of auxiliary rdi due to uneq is inhibited. nolopardi: the nolopardi bit is an active high auxiliary rdi insertion disable. when nolopardi is set high, ardi is not reported on rad nor in the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in loss of pointer state. nolopardi has precedence over tiuardi, timardi, psluardi and pslmardi. when nolopardi is set low, reporting of rdi is according to tiuardi, timardi, psluardi and pslmardi and the associated alarm states. noaisardi: the noaisardi bit is an active high auxiliary rdi insertion disable. when noaisardi is set high, auxiliary rdi is not reported on rad nor in the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in incoming ais state. noaisardi has precedence over tiuardi, timardi, psluardi and pslmardi. when noaisardi is set low, reporting of rdi is according to tiuardi, timardi, psluardi and pslmardi and the associated alarm states.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 156 nolomardi: the nolomardi bit is an active high auxiliary rdi insertion disable. when nolomardi is set high, ardi is not reported on rad nor in the v5 byte (g1 byte in tu3 mode) of the outgoing data stream for all tributaries that are in loss of multiframe state. when nolomardi is set low, reporting of rdi is according to tiuardi, timardi, psluardi and pslmardi and the associated alarm states.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 157 register 13h: stp tributary path defect indication control bit type function default bit 7 unused x bit 6 r/w loppdi 0 bit 5 r/w aispdi 0 bit 4 r/w uneqpdi 0 bit 3 r/w pdivpdi 0 bit 2 unused x bit 1 unused x bit 0 unused x this register controls the insertion of tributary path defect indications (pdi) on the receive alarm port (rad) as a result of tributary pointer alarms, tributary unequipped alarms, and tributary path defect indication alarms. pdivpdi: the pdivpdi bit is an active high path pdi insertion enable. when pdivpdi is set high, pdi-p is reported on rad when tributary path defect indication is detected in the tributary path signal label of the associated incoming tributary. when pdivpdi is set low, reporting of path pdi due to pdi-v is inhibited. uneqpdi: the uneqpdi bit is an active high path pdi insertion enable. when uneqpdi is set high, pdi-p is reported on rad when tributary unequipped indication ('b000) is detected in the tributary path signal label of the associated incoming tributary. when uneqpdi is set low, reporting of path pdi due to uneq is inhibited. aispdi: the aispdi bit is an active high path pdi insertion enable. when aispdi is set high, pdi-p is reported on rad when the associated incoming tributary is in ais state. when aispdi is set low, reporting of path pdi due to ais is inhibited.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 158 loppdi: the loppdi bit is an active high path pdi insertion enable. when loppdi is set high, pdi-p is reported on rad when the associated incoming tributary is in loss of pointer state. when loppdi is set low, reporting of path pdi due to lop is inhibited.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 159 register 14h: stp input signal activity monitor #2 bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w reserved x bit 3 r iaisa x bit 2 r itpla x bit 1 r itv5a x bit 0 r hsclka x this register, along with the stp input signal activity monitor #1, accumulation trigger register, provides activity monitoring on tupp+622 input signals. when a monitored input signal makes a low to high transition, the corresponding register bit is set high. the bit will remain high until this register is read, at which point, all the bits in this register are cleared. a lack of transitions is indicated by the corresponding register bit reading low. this register should be read periodically to detect for stuck at conditions. hsclka: the hsclk active (hsclka) bit monitors for low to high transitions on the hsclk input. hsclka is set high on a rising edge of hsclk, and is set low when this register is read. itv5a: the itv5 active (itv5a) bit monitors for low to high transitions on the corresponding itv5 input. itv5a is set high on a rising edge of itv5, and is set low when this register is read. itpla: the itpl active (itpla) bit monitors for low to high transitions on the corresponding itpl input. itpla is set high on a rising edge of itpl, and is set low when this register is read.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 160 iaisa: the iais active (iaisa) bit monitors for low to high transitions on the corresponding iais input. iaisa is set high on a rising edge of iais, and is set low when this register is read.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 161 register 15h: stp outgoing pointer lsb bit type function default bit 7 r/w optr[7] 0 bit 6 r/w optr[6] 0 bit 5 r/w optr[5] 0 bit 4 r/w optr[4] 0 bit 3 r/w optr[3] 1 bit 2 r/w optr[2] 0 bit 1 r/w optr[1] 1 bit 0 r/w optr[0] 0 register 16h: stp outgoing pointer msb bit type function default bit 7 r/w reserved 0 bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r/w optr[9] 1 bit 0 r/w optr[8] 0 optr[9:0]: the optr[9:0] bits are used to set an arbitrary active offset value in the corresponding outgoing (stm-1) stream. the arbitrary au3/au4 pointer value is transferred by writing to the stp outgoing pointer msb register. a legal value (i.e. 0 pointer value 782) results in new au3/au4 pointer(s) in the
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 162 corresponding outgoing (stm-1) stream. a value of greater than 782 has no effect. reserved: the reserved bit must be written with a logic 0 for proper operation of the tupp+622.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 163 register 17h: stp vtpp #1 configuration #2 bit type function default bit 7 r/w tugbyp 0 bit 6 r/w pibyp 0 bit 5 r/w noic1j1plbyp 0 bit 4 r/w h4sql 0 bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x this register is used to configure the major operational modes of vtpp #1. h4sql: the h4 squelch enable (h4sql) bit controls the insertion of the h4 byte in the outgoing sts-1 #1 (tug3 #1). when h4sql is set high, an all zeroes byte is inserted in the h4 position of the outgoing data stream. when h4sql is set low, normal tributary multiframe sequence in accordance with the corresponding otmf signal is inserted in the h4 byte of the outgoing data stream. noic1j1plbyp: the no ic1j1 and ipl bypass (noic1j1plbyp) bit controls the bypassing of the corresponding ic1j1 and ipl signals to the oc1j1v1 and opl outputs, respectively, when tugen is set low or bridge monitoring is enabled in sts-1 #1 (tug3 #1). when noic1j1plbyp is set low, the ic1j1 and ipl in the incoming data stream are transferred to the outgoing data stream unmodified. the amount of delay from the incoming to the outgoing data stream is a function of the internal data-path pipeline delay and gsclk_fp input. see the bypass functional timing diagram for details. when noic1j1plbyp is set high, ic1j1 and ipl are not bypassed, oc1j1v1 and opl are generated signals. noic1j1plbyp is ignored when tugen is set high or bridge monitoring is disabled in sts-1 #1 (tug3 #1).
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 164 pibyp: when set high, the pointer bypass enable (pibyp) bit configures the tributary payload processor to disable tributary pointer interpretation for the incoming sts-1 #1 (tug3 #1). pointer interpretation is performed by an external upstream pointer interpreter. tributary payload bytes are identified by the itpl signal and tributary payload frame boundaries are identified by the itv5 signal. tributary path ais can be indicated by the iais signal. when pibyp is set low, normal tributary pointer processing is performed on the incoming data stream. tugbyp: the tug bypass enable (tugbyp) bit enables bridge monitoring of tributaries in sts-1 #1 (tug3 #1). when tugbyp is set high, control and data signals in the incoming data stream are transferred to the outgoing data stream unmodified. the amount of delay from the incoming to the outgoing data stream is a function of the internal data-path pipeline delay and gsclk_fp input. see the bypass functional timing diagram for details. performance monitoring by vtpp #1, rtop #1 and rttb #1 remains active while consequential actions are disabled. when tugbyp is set low, sts-1 #1 (tug3 #1) is processed normally. tugbyp is ignored when tugen is set low. before the tug bypass is disabled, it is essential to first set the noic1j1plbyp bit in the stp vtpp #1 configuration #2 register high. this will ensure that the re-transmission of the corresponding input telecom bus signals, ic1j1 and ipl, to the output telecom bus is terminated gracefully.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 165 register 18h: stp vtpp #2 configuration #2 bit type function default bit 7 r/w tugbyp 0 bit 6 r/w pibyp 0 bit 5 r/w noic1j1plbyp 0 bit 4 r/w h4sql 0 bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x this register is used to configure the major operational modes of vtpp #2. h4sql: the h4 squelch enable (noic1j1plbyp) bit controls the insertion of the h4 byte in the outgoing sts-1 #2 (tug3 #2). when h4sql is set high, an all zeroes byte is inserted in the h4 position of the outgoing data stream. when h4sql is set low, normal tributary multiframe sequence in accordance with the corresponding otmf signal is inserted in the h4 byte of the outgoing data stream. noic1j1plbyp: the no ic1j1 and ipl bypass (noic1j1plbyp) bit controls the bypassing of the corresponding ic1j1 and ipl signals to the oc1j1v1 and opl outputs, respectively, when tugen is set low or bridge monitoring is enabled in sts-1 #2 (tug3 #2). when noic1j1plbyp is set low, the ic1j1 and ipl in the incoming data stream are transferred to the outgoing data stream unmodified. the amount of delay from the incoming to the outgoing data stream is a function of the internal data-path pipeline delay and gsclk_fp input. see the bypass functional timing diagram for details. when noic1j1plbyp is set high, ic1j1 and ipl are not bypassed, oc1j1v1 and opl are generated signals. noic1j1plbyp is ignored when tugen is set high or bridge monitoring is disabled in sts-1 #2 (tug3 #2).
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 166 pibyp: when set high, the pointer bypass enable (pibyp) bit configures the tributary payload processor to disable tributary pointer interpretation for the incoming sts-1 #2 (tug3 #2). pointer interpretation is performed by an external upstream pointer interpreter. tributary payload bytes are identified by the itpl signal and tributary payload frame boundaries are identified by the itv5 signal. tributary path ais can be indicated by the iais signal. when pibyp is set low, normal tributary pointer processing is performed on the incoming data stream. tugbyp: the tug bypass enable (tugbyp) bit enables bridge monitoring of tributaries in sts-1 #2 (tug3 #2). when tugbyp is set high, control and data signals in the incoming data stream are transferred to the outgoing data stream unmodified. the amount of delay from the incoming to the outgoing data stream is a function of the internal data-path pipeline delay and gsclk_fp input. see the bypass functional timing diagram for details. performance monitoring by vtpp #2, rtop #2 and rttb #2 remains active while consequential actions are disabled. when tugbyp is set low, sts-1 #2 (tug3 #2) is processed normally. tugbyp is ignored when tugen is set low. before the tug bypass is disabled, it is essential to first set the noic1j1plbyp bit in the stp vtpp #2 configuration #2 register high. this will ensure that the re-transmission of the corresponding input telecom bus signals, ic1j1 and ipl, to the output telecom bus is terminated gracefully.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 167 register 19h: stp vtpp #3 configuration #2 bit type function default bit 7 r/w tugbyp 0 bit 6 r/w pibyp 0 bit 5 r/w noic1j1plbyp 0 bit 4 r/w h4sql 0 bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x this register is used to configure the major operational modes of vtpp #3. h4sql: the h4 squelch enable (noic1j1plbyp) bit controls the insertion of the h4 byte in the outgoing sts-1 #3 (tug3 #3). when h4sql is set high, an all zeroes byte is inserted in the h4 position of the outgoing data stream. when h4sql is set low, normal tributary multiframe sequence in accordance with the corresponding otmf signal is inserted in the h4 byte of the outgoing data stream. noic1j1plbyp: the no ic1j1 and ipl bypass (noic1j1plbyp) bit controls the bypassing of the corresponding ic1j1 and ipl signals to the oc1j1v1 and opl outputs, respectively, when tugen is set low or bridge monitoring is enabled in sts-1 #3 (tug3 #3). when noic1j1plbyp is set low, the ic1j1 and ipl in the incoming data stream are transferred to the outgoing data stream unmodified. the amount of delay from the incoming to the outgoing data stream is a function of the internal data-path pipeline delay and gsclk_fp input. see the bypass functional timing diagram for details. when noic1j1plbyp is set high, ic1j1 and ipl are not bypassed, oc1j1v1 and opl are generated signals. noic1j1plbyp is ignored when tugen is set high or bridge monitoring is disabled in sts-1 #3 (tug3 #3).
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 168 pibyp: when set high, the pointer bypass enable (pibyp) bit configures the tributary payload processor to disable tributary pointer interpretation for the incoming sts-1 #3 (tug3 #3). pointer interpretation is performed by an external upstream pointer interpreter. tributary payload bytes are identified by the itpl signal and tributary payload frame boundaries are identified by the itv5 signal. tributary path ais can be indicated by the iais signal. when pibyp is set low, normal tributary pointer processing is performed on the incoming data stream. tugbyp: the tug bypass enable (tugbyp) bit enables bridge monitoring of tributaries in sts-1 #3 (tug3 #3). when tugbyp is set high, control and data signals in the incoming data stream are transferred to the outgoing data stream unmodified. the amount of delay from the incoming to the outgoing data stream is a function of the internal data-path pipeline delay and gsclk_fp input. see the bypass functional timing diagram for details. performance monitoring by vtpp #3, rtop #3 and rttb #3 remains active while consequential actions are disabled. when tugbyp is set low, sts-1 #3 (tug3 #3) is processed normally. tugbyp is ignored when tugen is set low. before the tug bypass is disabled, it is essential to first set the noic1j1plbyp bit in the stp vtpp #3 configuration #2 register high. this will ensure that the re-transmission of the corresponding input telecom bus signals, ic1j1 and ipl, to the output telecom bus is terminated gracefully.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 169 11.2 vtpp #1, vtpp #2 and vtpp #3 registers register 20h, 40h, 60h: vtpp, tu3 or tu #1 in tug2 #1, configuration and status bit type function default bit 7 r/w config[1] 1 bit 6 r/w config[0] 1 bit 5 r/w pf 0 bit 4 r lopv x bit 3 r/w alarme 0 bit 2 r/w dlop 0 bit 1 r/w iidle 0 bit 0 r/w ipais 0 in tu3 mode (tu3 bit in vtpp configuration register set high), this register reports the status and configures operational modes of the tu3 mapped into a tug3 handled by the vtpp. out of tu3 mode, this register reports the status and configures the operational modes of tu #1 in tug2 #1. ipais: the ipais bit enables the insertion of path ais for tributary tu #1 in tug2 #1 or tu3 depending on whether the vtpp is in tu3 mode. tributary path ais is inserted by forcing all ones into all tributary bytes. the ipais bit has no effect when iidle is set high. iidle: the iidle bit enables the insertion of path idle for tributary tu #1 in tug2 #1 or tu3 depending on whether the vtpp is in tu3 mode. when iidle is set high, tributary payload bytes, including v5 are replaced by an all-zero code. the v5 byte is set to all-zero to yield correct bip-2 and to indicate tributary unequipped. the outgoing pointer is forced to zero. the iidle bit has precedence over the ipais bit.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 170 dlop: the dlop bit allows downstream pointer processing elements to be diagnosed. when dlop is set high, the new data flag (ndf) field of the outgoing payload pointer in tributary tu #1 in tug2 #1 or tu3 depending on whether the vtpp is in tu3 mode, is inverted to cause downstream pointer processing elements to enter a loss of pointer state. the dlop bit has no effect when the ipais bit is set high. alarme: the alarme bit enables loss of pointer and path ais interrupts for tributary tu #1 in tug2 #1 or tu3 depending on whether the vtpp is in tu3 mode. when alarme is set high, an interrupt is generated upon entry to and exit from the lop and ais state of the pointer interpreter state diagram. interrupts due to ais and lop status change are masked when alarme is set low. lopv: the lopv bit indicates the loss of pointer status of tributary tu #1 in tug2 #1 or tu3 depending on whether the vtpp is in tu3 mode. pf: the pf bit enables pointer follower mode for tributary tu #1 in tug2 #1 or tu3 depending on whether the vtpp is in tu3 mode. in pointer follower mode, the tributary fifo dead-zone is collapsed so that any variation in fifo depth will result in an outgoing pointer justification event. any tu pointer justification event on the corresponding incoming tributary, or an au pointer justification event affecting this tributary will cause an outgoing pointer justification event. config[1:0]: the config[1:0] bits specify the tributary configuration of tributary group tug2 #1. the config[1:0] bits have no effect in tu3 mode. the configuration specified by the config[1:0] bits are selected as follows:
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 171 config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 172 register 21h-26h, 41h-46h, 61h-66h: vtpp, tu #1 in tug2 #2 to tug2 #7, configuration and status bit type function default bit 7 r/w config[1] 1 bit 6 r/w config[0] 1 bit 5 r/w pf 0 bit 4 r lopv x bit 3 r/w alarme 0 bit 2 r/w dlop 0 bit 1 r/w iidle 0 bit 0 r/w ipais 0 this set of registers reports the status and configures the operational modes of tu #1 in tug2 #2 to tug2 #7. these registers have no effect in tu3 mode. ipais: the ipais bit enables the insertion of path ais for tributary tu #1 in the corresponding tug2. tributary path ais is inserted by forcing all ones into all tributary bytes. the ipais bit has no effect when iidle is set high. iidle: the iidle bit enables the insertion of path idle for tributary tu #1 in the corresponding tug2 . when iidle is set high, tributary payload bytes, including v5 is replaced by an all-zero code. the v5 byte is set to all-zero to yield correct bip-2 and to indicate tributary unequipped. the outgoing pointer is forced to zero. the iidle bit has precedence over the ipais bit. dlop: the dlop bit allows downstream pointer processing elements to be diagnosed. when dlop is set high, the new data flag (ndf) field of the outgoing payload pointer in tributary tu #1 in the corresponding tug2 is inverted to cause downstream pointer processing elements to enter a loss of pointer state. the dlop bit has no effect when the ipais bit is set high.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 173 alarme: the alarme bit enables loss of pointer and path ais interrupts for tributary tu #1 in the corresponding tug2. when alarme is set high, an interrupt is generated upon entry to and exit from the lop and ais state of the pointer interpreter state diagram. interrupts due to ais and lop status change are masked when alarme is set low. lopv: the lopv bit indicates the loss of pointer status of tributary tu #1 in the corresponding tug2. pf: the pf bit enables pointer follower mode for tributary tu #1 in the corresponding tug2. in pointer follower mode, the tributary fifo dead-zone is collapsed so that any variation in fifo depth will result in an outgoing pointer justification event. any tu pointer justification event on the corresponding incoming tributary, or an au pointer justification event affecting this tributary will cause an outgoing pointer justification event. config[1:0]: the config[1:0] bits specify the tributary configuration of the tug2 tributary group. the config[1:0] bits have no effect in tu3 mode. the configuration specified by the config[1:0] bits are selected as follows: config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 174 register 27h, 47h, 67h: vtpp, tu3 or tu #1 in tug2 #1 to tug2 #7, lop interrupt bit type function default bit 7 r/w reserved 0 bit 6 r lop7i 0 bit 5 r lop6i 0 bit 4 r lop5i 0 bit 3 r lop4i 0 bit 2 r lop3i 0 bit 1 r lop2i 0 bit 0 r lop1i 0 this register is used to identify and acknowledge loss of pointer interrupts for the tributaries tu #1 in tug2 #1 to tug2 #7. it is also used to identify and acknowledge tu3 loss of pointer interrupts. lop1i: the lop1i bit identifies the source of loss of pointer interrupts. in tu3 mode, the lop1i bit reports and acknowledges lop interrupt of the tu3 pointer. out of tu3 mode, the lop1i bit reports and acknowledges lop interrupt of tu #1 in tug2 #1. interrupts are generated upon loss of pointer and upon re- acquisition. lop1i is set high when the corresponding loss of pointer event occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. lop1i remains valid when interrupts are not enabled (alarme set low) and may be polled to detect loss of pointer events. lop2i-lop7i: the lop2i to lop7i bits identify the source of loss of pointer interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. out of tu3 mode, the lop2i to lop7i bits report and acknowledge lop interrupt of tu #1 in tug2 #2 to tug2 #7, respectively. interrupts are generated upon loss of pointer and upon re-acquisition. an lop x i bit is set high when a loss of
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 175 pointer event on the associated tributary (tu #1 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. lop x i remains valid when interrupts are not enabled (alarme set low) and may be polled to detect loss of pointer events. reserved: the reserved bit must be written with a logic 0 for proper operation of the tupp+622.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 176 register 28h-2eh, 48h-4eh, 68h-6eh: vtpp, tu #2 in tug2 #1 to tug2 #7, configuration and status bit type function default bit 7 r config[1] 1 bit 6 r config[0] 1 bit 5 r/w pf 0 bit 4 r lopv x bit 3 r/w alarme 0 bit 2 r/w dlop 0 bit 1 r/w iidle 0 bit 0 r/w ipais 0 this set of registers reports the status and configures the operational modes of tu #2 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) mode, the associated register in this set has no effect. ipais: the ipais bit enables the insertion of path ais for tributary tu #2 in the corresponding tug2. tributary path ais is inserted by forcing all ones into all tributary bytes. the ipais bit has no effect when iidle is set high. iidle: the iidle bit enables the insertion of path idle for tributary tu #2 in the corresponding tug2. when iidle is set high, tributary payload bytes, including v5 is replaced by an all-zero code. the v5 byte is set to all-zero to yield correct bip-2 and to indicate tributary unequipped. the outgoing pointer is forced to zero. the iidle bit has precedence over the ipais bit. dlop: the dlop bit allows downstream pointer processing elements to be diagnosed. when dlop is set high, the new data flag (ndf) field of the outgoing payload pointer in tributary tu #2 in the corresponding tug2 is
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 177 inverted, causing downstream pointer processing elements to enter a loss of pointer state. the dlop bit has no effect when the ipais bit is set high. alarme: the alarme bit enables loss of pointer and path ais interrupts for tributary tu #2 in the corresponding tug2. when alarme is set high, an interrupt is generated upon entry to and exit from the lop and ais state of the pointer interpreter state diagram. interrupts due to ais and lop status change are masked when alarme is set low. lopv: the lopv bit indicates the loss of pointer status of tributary tu #2 in the corresponding tug2. pf: the pf bit enables pointer follower mode for tributary tu #2 in the corresponding tug2. in pointer follower mode, the tributary fifo dead-zone is collapsed so that any variation in fifo depth will result in an outgoing pointer justification event. any tu pointer justification event on the corresponding incoming tributary, or an au pointer justification event affecting this tributary will cause an outgoing pointer justification event. config[1:0]: the config[1:0] bits are read-only and reflect the values written into the corresponding register of tu #1. the configuration specified by the config[1:0] bits are selected as follows: config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 178 register 2fh, 4fh, 6fh: vtpp, tu #2 in tug2 #1 to tug2 #7, lop interrupt bit type function default bit 7 unused x bit 6 r lop7i 0 bit 5 r lop6i 0 bit 4 r lop5i 0 bit 3 r lop4i 0 bit 2 r lop3i 0 bit 1 r lop2i 0 bit 0 r lop1i 0 this register is used to identify and acknowledge loss of pointer interrupts for the tributaries tu #3 in tug2 #1 to tug2 #7. lop1i-lop7i: the lop1i to lop7i bits identify the source of loss of pointer interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) mode, the associated lop x i bit is unused and will return a logic 0 when read. when operational, the lop1i to lop7i bits report and acknowledge lop interrupts of tu #2 in tug2 #1 to tug2 #7, respectively. interrupts are generated upon loss of pointer and upon re-acquisition. an lop x i bit is set high when a loss of pointer event on the associated tributary occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. lop x i remains valid when interrupts are not enabled (alarme set low) and may be polled to detect loss of pointer events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 179 register 30h-36h, 50h-56h, 70h-76h: vtpp, tu #3 in tug2 #1 to tug2 #7, configuration and status bit type function default bit 7 r config[1] 1 bit 6 r config[0] 1 bit 5 r/w pf 0 bit 4 r lopv x bit 3 r/w alarme 0 bit 2 r/w dlop 0 bit 1 r/w iidle 0 bit 0 r/w ipais 0 this set of registers reports the status and configures the operational modes of tu #3 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) or vt3 mode, the associated register in this set has no effect. ipais: the ipais bit enables the insertion of path ais for tributary tu #3 in the corresponding tug2. tributary path ais is inserted by forcing all ones into all tributary bytes. the ipais bit has no effect when iidle is set high. iidle: the iidle bit enables the insertion of path idle for tributary tu #3 in the corresponding tug2. when iidle is set high, tributary payload bytes, including v5 is replaced by an all-zero code. the v5 byte is set to all-zero to yield correct bip-2 and to indicate tributary unequipped. the outgoing pointer is forced to zero. the iidle bit has precedence over the ipais bit. dlop: the dlop bit allows downstream pointer processing elements to be diagnosed. when dlop is set high, the new data flag (ndf) field of the outgoing payload pointer in tributary tu #3 in the corresponding tug2 is
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 180 inverted, causing downstream pointer processing elements to enter a loss of pointer state. the dlop bit has no effect when the ipais bit is set high. alarme: the alarme bit enables loss of pointer and path ais interrupts for tributary tu #3 in the corresponding tug2. when alarme is set high, an interrupt is generated upon entry to and exit from the lop and ais state of the pointer interpreter state diagram. interrupts due to ais and lop status change are masked when alarme is set low. lopv: the lopv bit indicates the loss of pointer status of tributary tu #3 in the corresponding tug2. pf: the pf bit enables pointer follower mode for tributary tu #3 in the corresponding tug2. in pointer follower mode, the tributary fifo dead-zone is collapsed so that any variation in fifo depth will result in an outgoing pointer justification event. any tu pointer justification event on the corresponding incoming tributary, or an au pointer justification event affecting this tributary will cause an outgoing pointer justification event. config[1:0]: the config[1:0] bits are read-only and reflect the values written into the corresponding register of tu #1. the configuration specified by the config[1:0] bits are selected as follows: config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 181 register 37h, 57h, 77h: vtpp, tu #3 in tug2 #1 to tug2 #7, lop interrupt bit type function default bit 7 unused x bit 6 r lop7i 0 bit 5 r lop6i 0 bit 4 r lop5i 0 bit 3 r lop4i 0 bit 2 r lop3i 0 bit 1 r lop2i 0 bit 0 r lop1i 0 this register is used to identify and acknowledge loss of pointer interrupts for the tributaries tu #2 in tug2 #1 to tug2 #7. lop1i-lop7i: the lop1i to lop7i bits identify the source of loss of pointer interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) or vt3 mode, the associated lop x i bit is unused and will return a logic 0 when read. when operational, the lop1i to lop7i bits report and acknowledge lop interrupts of tu #3 in tug2 #1 to tug2 #7, respectively. interrupts are generated upon loss of pointer and upon re-acquisition. an lop x i bit is set high when a loss of pointer event on the associated tributary occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. lop x i remains valid when interrupts are not enabled (alarme set low) and may be polled to detect loss of pointer events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 182 register 38h-3eh, 58h-5eh, 78h-7eh: vtpp, tu #4 in tug2 #1 to tug2 #7, configuration and status bit type function default bit 7 r config[1] 1 bit 6 r config[0] 1 bit 5 r/w pf 0 bit 4 r lopv x bit 3 r/w alarme 0 bit 2 r/w dlop 0 bit 1 r/w iidle 0 bit 0 r/w ipais 0 this set of registers reports the status and configures the operational modes of tu #4 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6), vt3 or, tu12 (vt2) mode, the associated register in this set has no effect. ipais: the ipais bit enables the insertion of path ais for tributary tu #4 in the corresponding tug2. tributary path ais is inserted by forcing all ones into all tributary bytes. the ipais bit has no effect when iidle is set high. iidle: the iidle bit enables the insertion of path idle for tributary tu #4 in the corresponding tug2. when iidle is set high, tributary payload bytes, including v5 is replaced by an all-zero code. the v5 byte is set to all-zero to yield correct bip-2 and to indicate tributary unequipped. the outgoing pointer is forced to zero. the iidle bit has precedence over the ipais bit. dlop: the dlop bit allows downstream pointer processing elements to be diagnosed. when dlop is set high, the new data flag (ndf) field of the outgoing payload pointer in tributary tu #4 in the corresponding tug2 is
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 183 inverted, causing downstream pointer processing elements to enter a loss of pointer state. the dlop bit has no effect when the ipais bit is set high. alarme: the alarme bit enables loss of pointer and path ais interrupts for tributary tu #4 in the corresponding tug2. when alarme is set high, an interrupt is generated upon entry to and exit from the lop and ais state of the pointer interpreter state diagram. interrupts due to ais and lop status change are masked when alarme is set low. lopv: the lopv bit indicates the loss of pointer status of tributary tu #4 in the corresponding tug2. pf: the pf bit enables pointer follower mode for tributary tu #4 in the corresponding tug2. in pointer follower mode, the tributary fifo dead-zone is collapsed so that any variation is fifo depth will result in an outgoing pointer justification event. any tu pointer justification event on the corresponding incoming tributary, or an au pointer justification event affecting this tributary will cause an outgoing pointer justification event. config[1:0]: the config[1:0] bits are read-only and reflect the values written into the corresponding register of tu #1. the configuration specified by the config[1:0] bits are selected as follows: config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 184 register 3fh, 5fh, 7fh: vtpp, tu #4 in tug2 #1 to tug2 #7, lop interrupt bit type function default bit 7 unused x bit 6 r lop7i 0 bit 5 r lop6i 0 bit 4 r lop5i 0 bit 3 r lop4i 0 bit 2 r lop3i 0 bit 1 r lop2i 0 bit 0 r lop1i 0 this register is used to identify and acknowledge loss of pointer interrupts for the tributaries tu #4 in tug2 #1 to tug2 #7. lop1i-lop7i: the lop1i to lop7i bits identify the source of loss of pointer interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6), vt3, or tu12 (vt2) mode, the associated lop x i bit is unused and will return a logic 0 when read. when operational, the lop1i to lop7i bits report and acknowledge lop interrupt of tu #4 in tug2 #1 to tug2 #7, respectively. interrupts are generated upon loss of pointer and upon re-acquisition. an lop x i bit is set high when a loss of pointer event on the associated tributary occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. lop x i remains valid when interrupts are not enabled (alarme set low) and may be polled to detect loss of pointer events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 185 register a0h, c0h, e0h: vtpp, tu3 or tu #1 in tug2 #1, alarm status bit type function default bit 7 r ss[1] x bit 6 r ss[0] x bit 5 r njei x bit 4 r pjei x bit 3 r esei x bit 2 r/w pee 0 bit 1 r aisv x bit 0 r/w relayais 0 in tu3 mode (tu3 bit in vtpp configuration register set high), this register reports the alarm status of the tu3 mapped into a tug3 handled by the vtpp. out of tu3 mode, this register reports the alarm status of tu #1 in tug2 #1. relayais: the relayais bit controls the number of consecutive ais_ind indications required to enter the ais state for tributary tu #1 in tug2 #1 or tu3 depending on whether the vtpp is in tu3 mode. when relayais is set high, ais is declared upon receipt of a single ais_ind indication. when relayais is set low, ais is declared after 3 consecutive ais_ind indications. aisv: the aisv bit indicates the tributary path ais status of tributary tu #1 in tug2 #1 or tu3 depending on whether the vtpp is in tu3 mode. pee: the pee bit enables pointer event interrupts for tributary tu #1 in tug2 #1 or tu3 depending on whether the vtpp is in tu3 mode. when pee is set high, an interrupt is generated upon detection of fifo underflows and overflows, upon detection of incoming pointer justification events when the monis bit is set high and upon detection of outgoing pointer justification events when the
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 186 monis bit is set low. interrupts due to elastic store errors and pointer justification events are masked when pee is set low. esei: the esei bit reports and acknowledges the status of elastic store error interrupts for tributary tu #1 in tug2 #1 or tu3 depending on whether the vtpp is in tu3 mode. interrupts are generated upon fifo underflows and overflows. esei is set high when an elastic store error occurs and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. esei remains valid when interrupts are not enabled (pee set low) and may be polled to detect elastic store error events. pjei: the pjei bit reports and acknowledges the status of the positive pointer justification event interrupts for tributary tu #1 in tug2 #1 or tu3 depending on whether the vtpp is in tu3 mode. when the monis bit is set high, interrupts are generated upon reception of a positive pointer justification event in the incoming stream. when the monis bit is set low, interrupts are generated upon generation of a positive pointer justification event in the outgoing stream. pjei is set high when a positive pointer justification event occurs in the monitored stream and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pjei remains valid when interrupts are not enabled (pee set low) and may be polled to detect positive pointer justification events. njei: the njei bit reports and acknowledges the status of the negative pointer justification event interrupts for tributary tu #1 in tug2 #1 or tu3 depending on whether the vtpp is in tu3 mode. when the monis bit is set high, interrupts are generated upon reception of a negative pointer justification event in the incoming stream. when the monis bit is set low, interrupts are generated upon generation of a negative pointer justification event in the outgoing stream. njei is set high when a negative pointer justification event occurs in the monitored stream and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. njei remains valid when interrupts are not enabled (pee set low) and may be polled to detect negative pointer justification events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 187 ss[1:0]: the ss[1:0] bits report the value of the size bits in the v1 byte of tributary tu #1 in tug2 #1 or the h1 byte of tributary tu3 depending on whether the vtpp is in tu3 mode. the ss[1:0] bits are not filtered and must be software de-bounced.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 188 register a1h-a6h, c1h-c6h, e1h-e6h: vtpp, tu #1 in tug2 #2 to tug2 #7, alarm status bit type function default bit 7 r ss[1] x bit 6 r ss[0] x bit 5 r njei x bit 4 r pjei x bit 3 r esei x bit 2 r/w pee 0 bit 1 r aisv x bit 0 r/w relayais 0 this set of registers reports the alarm status of tu #1 in tug2 #2 to tug2 #7. these registers have no effect in tu3 mode. relayais: the relayais bit controls the number of consecutive ais_ind indications required to enter the ais state for tributary tu #1 in the corresponding tug2. when relayais is set high, ais is declared upon receipt of a single ais_ind indication. when relayais is set low, ais is declared after 3 consecutive ais_ind indications. aisv: the aisv bit indicates the tributary path ais status of tributary tu #1 in the corresponding tug2. pee: the pee bit enables pointer event interrupts for tributary tu #1 in the corresponding tug2. when pee is set high, an interrupt is generated upon detection of fifo underflows and overflows, upon detection of incoming pointer justification events when the monis bit is set high and upon detection of outgoing pointer justification events when the monis bit is set low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 189 interrupts due to elastic store errors and pointer justification events are masked when pee is set low. esei: the esei bit reports and acknowledges the status of elastic store error interrupts for tributary tu #1 in the corresponding tug2. interrupts are generated upon fifo underflows and overflows. esei is set high when an elastic store error occurs and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. esei remains valid when interrupts are not enabled (pee set low) and may be polled to detect elastic store error events. pjei: the pjei bit reports and acknowledges the status of the positive pointer justification event interrupts for tributary tu #1 in the corresponding tug2. when the monis bit is set high, interrupts are generated upon reception of a positive pointer justification event in the incoming stream. when the monis bit is set low, interrupts are generated upon generation of a positive pointer justification event in the outgoing stream. pjei is set high when a positive pointer justification event occurs in the monitored stream and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pjei remains valid when interrupts are not enabled (pee set low) and may be polled to detect positive pointer justification events. njei: the njei bit reports and acknowledges the status of the negative pointer justification event interrupts for tributary tu #1 in the corresponding tug2. when the monis bit is set high, interrupts are generated upon reception of a negative pointer justification event in the incoming stream. when the monis bit is set low, interrupts are generated upon generation of a negative pointer justification event in the outgoing stream. njei is set high when a negative pointer justification event occurs in the monitored stream and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. njei remains valid when interrupts are not enabled (pee set low) and may be polled to detect negative pointer justification events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 190 ss[1:0]: the ss[1:0] bits report the value of the size bits in the v1 byte of tributary tu #1 in the corresponding tug2. the ss[1:0] bits are not filtered and must be software de-bounced.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 191 register a7h, c7h, e7h: vtpp, tu3 or tu #1 in tug2 #1 to tug2 #7, ais interrupt bit type function default bit 7 unused x bit 6 r ais7i 0 bit 5 r ais6i 0 bit 4 r ais5i 0 bit 3 r ais4i 0 bit 2 r ais3i 0 bit 1 r ais2i 0 bit 0 r ais1i 0 this register is used to identify and acknowledge alarm indication signal interrupts for the tributaries tu #1 in tug2 #1 to tug2 #7. it is also used to identify and acknowledge tu3 ais interrupts. ais1i: the ais1i bit identifies the source of tributary path ais interrupts. in tu3 mode, the ais1i bit reports and acknowledges ais interrupt of the tu3 stream. out of tu3 mode, the ais1i bit reports and acknowledges ais interrupt of tu #1 in tug2 #1. interrupts are generated upon detection and removal of tributary path ais alarm. ais1i is set high when the corresponding tributary path ais event occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. ais1i remains valid when interrupts are not enabled (alarme set low) and may be polled to detect tributary path ais events. ais2i-ais7i: the ais2i to ais7i bits identify the source of tributary path ais interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. out of tu3 mode, the ais2i to ais7i bits report and acknowledge ais interrupt of tu #1 in tug2 #2 to tug2 #7, respectively. interrupts are generated upon detection and removal of tributary path ais. an ais x i bit is set high when a
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 192 tributary path ais event on the associated tributary (tu #1 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. ais x i remains valid when interrupts are not enabled (alarme set low) and may be polled to detect tributary path ais events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 193 register a8h-aeh, c8h-ceh, e8h-eeh: vtpp, tu #2 in tug2 #1 to tug2 #7, alarm status bit type function default bit 7 r ss[1] x bit 6 r ss[0] x bit 5 r njei x bit 4 r pjei x bit 3 r esei x bit 2 r/w pee 0 bit 1 r aisv x bit 0 r/w relayais 0 this set of registers reports the alarm status of tu #2 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) mode, the associated register in this set has no effect. relayais: the relayais bit controls the number of consecutive ais_ind indications required to enter the ais state for tributary tu #2 in the corresponding tug2. when relayais is set high, ais is declared upon receipt of a single ais_ind indication. when relayais is set low, ais is declared after 3 consecutive ais_ind indications. aisv: the aisv bit indicates the tributary path ais status of tributary tu #2 in the corresponding tug2. pee: the pee bit enables pointer event interrupts for tributary tu #2 in the corresponding tug2. when pee is set high, an interrupt is generated upon detection of fifo underflows and overflows, upon detection of incoming pointer justification events when the monis bit is set high and upon detection
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 194 of outgoing pointer justification events when the monis bit is set low. interrupts due to elastic store errors and pointer justification events are masked when pee is set low. esei: the esei bit reports and acknowledges the status of elastic store error interrupts for tributary tu #2 in the corresponding tug2. interrupts are generated upon fifo underflows and overflows. esei is set high when an elastic store error occurs and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. esei remains valid when interrupts are not enabled (pee set low) and may be polled to detect elastic store error events. pjei: the pjei bit reports and acknowledges the status of the positive pointer justification event interrupts for tributary tu #2 in the corresponding tug2. when the monis bit is set high, interrupts are generated upon reception of a positive pointer justification event in the incoming stream. when the monis bit is set low, interrupts are generated upon generation of a positive pointer justification event in the outgoing stream. pjei is set high when a positive pointer justification event occurs in the monitored stream and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pjei remains valid when interrupts are not enabled (pee set low) and may be polled to detect positive pointer justification events. njei: the njei bit reports and acknowledges the status of the negative pointer justification event interrupts for tributary tu #2 in the corresponding tug2. when the monis bit is set high, interrupts are generated upon reception of a negative pointer justification event in the incoming stream. when the monis bit is set low, interrupts are generated upon generation of a negative pointer justification event in the outgoing stream. njei is set high when a negative pointer justification event occurs in the monitored stream and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. njei remains valid when interrupts are not enabled (pee set low) and may be polled to detect negative pointer justification events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 195 ss[1:0]: the ss[1:0] bits report the value of the size bits in the v1 byte of tributary tu #2 in the corresponding tug2. the ss[1:0] bits are not filtered and must be software de-bounced.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 196 register afh, cfh, efh: vtpp, tu #2 in tug2 #1 to tug2 #7 ais interrupt bit type function default bit 7 unused x bit 6 r ais7i 0 bit 5 r ais6i 0 bit 4 r ais5i 0 bit 3 r ais4i 0 bit 2 r ais3i 0 bit 1 r ais2i 0 bit 0 r ais1i 0 this register is used to identify and acknowledge tributary path ais interrupts for the tributaries tu #2 in tug2 #1 to tug2 #7. ais1i-ais7i: the ais1i to ais7i bits identify the source of tributary path ais interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) mode, the associated ais x i bit is unused and will return a logic 0 when read. when operational, the ais1i to ais7i bits report and acknowledge ais interrupt of tu #2 in tug2 #1 to tug2 #7, respectively. interrupts are generated upon detection and removal of tributary path ais alarm. an ais x i bit is set high when a tributary path ais event on the associated tributary occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. ais x i remains valid when interrupts are not enabled (alarme set low) and may be polled to detect tributary path ais events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 197 register b0h-b6h, d0h-d6h, f0h-f6h: vtpp, tu #3 in tug2 #1 to tug2 #7, alarm status bit type function default bit 7 r ss[1] x bit 6 r ss[0] x bit 5 r njei x bit 4 r pjei x bit 3 r esei x bit 2 r/w pee 0 bit 1 r aisv x bit 0 r/w relayais 0 this set of registers reports the status and configures the operational modes of tu #3 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) or vt3 mode, the associated register in this set has no effect. relayais: the relayais bit controls the number of consecutive ais_ind indications required to enter the ais state for tributary tu #3 in the corresponding tug2. when relayais is set high, ais is declared upon receipt of a single ais_ind indication. when relayais is set low, ais is declared after 3 consecutive ais_ind indications. aisv: the aisv bit indicates the tributary path ais status of tributary tu #3 in the corresponding tug2. pee: the pee bit enables pointer event interrupts for tributary tu #3 in the corresponding tug2. when pee is set high, an interrupt is generated upon detection of fifo underflows and overflows, upon detection of incoming pointer justification events when the monis bit is set high and upon detection
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 198 of outgoing pointer justification events when the monis bit is set low. interrupts due to elastic store errors and pointer justification events are masked when pee is set low. esei: the esei bit reports and acknowledges the status of elastic store error interrupts for tributary tu #3 in the corresponding tug2. interrupts are generated upon fifo underflows and overflows. esei is set high when an elastic store error occurs and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. esei remains valid when interrupts are not enabled (pee set low) and may be polled to detect elastic store error events. pjei: the pjei bit reports and acknowledges the status of the positive pointer justification event interrupts for tributary tu #3 in the corresponding tug2. when the monis bit is set high, interrupts are generated upon reception of a positive pointer justification event in the incoming stream. when the monis bit is set low, interrupts are generated upon generation of a positive pointer justification event in the outgoing stream. pjei is set high when a positive pointer justification event occurs in the monitored stream and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pjei remains valid when interrupts are not enabled (pee set low) and may be polled to detect positive pointer justification events. njei: the njei bit reports and acknowledges the status of the negative pointer justification event interrupts for tributary tu #3 in the corresponding tug2. when the monis bit is set high, interrupts are generated upon reception of a negative pointer justification event in the incoming stream. when the monis bit is set low, interrupts are generated upon generation of a negative pointer justification event in the outgoing stream. njei is set high when a negative pointer justification event occurs in the monitored stream and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. njei remains valid when interrupts are not enabled (pee set low) and may be polled to detect negative pointer justification events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 199 ss[1:0]: the ss[1:0] bits report the value of the size bits in the v1 byte of tributary tu #3 in the corresponding tug2. the ss[1:0] bits are not filtered and must be software de-bounced.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 200 register b7h, d7h, f7h: vtpp, tu #3 in tug2 #1 to tug2 #7, ais interrupt bit type function default bit 7 unused x bit 6 r ais7i 0 bit 5 r ais6i 0 bit 4 r ais5i 0 bit 3 r ais4i 0 bit 2 r ais3i 0 bit 1 r ais2i 0 bit 0 r ais1i 0 this register is used to identify and acknowledge tributary path ais interrupts for the tributaries tu #3 in tug2 #1 to tug2 #7. ais1i-ais7i: the ais1i to ais7i bits identify the source of tributary path ais interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) or vt3 mode, the associated ais x i bit is unused and will return a logic 0 when read. when operational, the ais1i to ais7i bits report and acknowledge ais interrupt of tu #3 in tug2 #1 to tug2 #7, respectively. interrupts are generated upon detection and removal of tributary path ais alarm. an ais x i bit is set high when a tributary path ais event on the associated tributary occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. ais x i remains valid when interrupts are not enabled (alarme set low) and may be polled to detect tributary path ais events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 201 register b8h-beh, d8h-deh, f8h-feh: vtpp, tu #4 in tug2 #1 to tug2 #7, alarm status bit type function default bit 7 r ss[1] x bit 6 r ss[0] x bit 5 r njei x bit 4 r pjei x bit 3 r esei x bit 2 r/w pee 0 bit 1 r aisv x bit 0 r/w relayais 0 this set of registers reports the alarm status of tu #4 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6), vt3 or tu12 (vt2) mode, the associated register in this set has no effect. relayais: the relayais bit controls the number of consecutive ais_ind indications required to enter the ais state for tributary tu #4 in the corresponding tug2. when relayais is set high, ais is declared upon receipt of a single ais_ind indication. when relayais is set low, ais is declared after 3 consecutive ais_ind indications. aisv: the aisv bit indicates the tributary path ais status of tributary tu #4 in the corresponding tug2. pee: the pee bit enables pointer event interrupts for tributary tu #4 in the corresponding tug2. when pee is set high, an interrupt is generated upon detection of fifo underflows and overflows, upon detection of incoming pointer justification events when the monis bit is set high and upon detection
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 202 of outgoing pointer justification events when the monis bit is set low. interrupts due to elastic store errors and pointer justification events are masked when pee is set low. esei: the esei bit reports and acknowledges the status of elastic store error interrupts for tributary tu #4 in the corresponding tug2. interrupts are generated upon fifo underflows and overflows. esei is set high when an elastic store error occurs and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. esei remains valid when interrupts are not enabled (pee set low) and may be polled to detect elastic store error events. pjei: the pjei bit reports and acknowledges the status of the positive pointer justification event interrupts for tributary tu #4 in the corresponding tug2. when the monis bit is set high, interrupts are generated upon reception of a positive pointer justification event in the incoming stream. when the monis bit is set low, interrupts are generated upon generation of a positive pointer justification event in the outgoing stream. pjei is set high when a positive pointer justification event occurs in the monitored stream and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pjei remains valid when interrupts are not enabled (pee set low) and may be polled to detect positive pointer justification events. njei: the njei bit reports and acknowledges the status of the negative pointer justification event interrupts for tributary tu #4 in the corresponding tug2. when the monis bit is set high, interrupts are generated upon reception of a negative pointer justification event in the incoming stream. when the monis bit is set low, interrupts are generated upon generation of a negative pointer justification event in the outgoing stream. njei is set high when a negative pointer justification event occurs in the monitored stream and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. njei remains valid when interrupts are not enabled (pee set low) and may be polled to detect negative pointer justification events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 203 ss[1:0]: the ss[1:0] bits report the value of the size bits in the v1 byte of tributary tu #4 in the corresponding tug2. the ss[1:0] bits are not filtered and must be software de-bounced.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 204 register bfh, dfh, ffh: vtpp, tu #4 in tug2 #1 to tug2 #7, ais interrupt bit type function default bit 7 unused x bit 6 r ais7i 0 bit 5 r ais6i 0 bit 4 r ais5i 0 bit 3 r ais4i 0 bit 2 r ais3i 0 bit 1 r ais2i 0 bit 0 r ais1i 0 this register is used to identify and acknowledge tributary path ais interrupts for the tributaries tu #4 in tug2 #1 to tug2 #7. ais1i-ais7i: the ais1i to ais7i bits identify the source of tributary path ais interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6), vt3 or tu12 (vt2) mode, the associated ais x i bit is unused and will return a logic 0 when read. when operational, the ais1i to ais7i bits report and acknowledge ais interrupt of tu #4 in tug2 #1 to tug2 #7, respectively. interrupts are generated upon detection and removal of tributary path ais alarm. an ais x i bit is set high when a tributary path ais event on the associated tributary occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. ais x i remains valid when interrupts are not enabled (alarme set low) and may be polled to detect tributary path ais events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 205 11.3 rtop #1, rtop #2 and rtop #3 registers register 100h, 200h, 300h: rtop, tu3 or tu #1 in tug2 #1, configuration bit type function default bit 7 r/w config[1] 1 bit 6 r/w config[0] 1 bit 5 r/w blkbip 0 bit 4 r/w pslue 0 bit 3 r/w pslme 0 bit 2 r/w copsle 0 bit 1 r/w rfie 0 bit 0 r/w rdie 0 in tu3 mode (tu3 bit in vtpp configuration register set high), this register reports the status and configures operational modes of the tu3 mapped into a tug3 handled by the rtop. out of tu3 mode, this register reports the status and configures the operational modes of tu #1 in tug2 #1. rdie: the rdie bit enables the remote defect indication interrupt for tributary tu #1 in tug2 #1 or tu3 depending on whether the rtop is in tu3 mode. when rdie is set high, an interrupt is generated upon changes of rdi status. interrupts due to rdi status change are masked when rdie is set low. the rdi status is derived from bit 8 of the v5 byte when rdiz7en is set low and from bits 5 to 7 of the z7 byte when rdiz7en is set high. rfie: the rfie bit enables the remote failure indication interrupt for tributary tu #1 in tug2 #1 or tu3 depending on whether the rtop is in tu3 mode. when rdiz7en is set low, an interrupt is generated upon assertion and negation events of the rfiv bit when rfie is set high. interrupts due to rfiv status change are masked when rfie is set low. when rdiz7en is set high, rfie
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 206 is ignored. the rfie bit is not used when the rtop is in tu3 mode is enabled. copsle: the copsle bit enables the change of tributary path signal label interrupt for tributary tu #1 in tug2 #1 or tu3. when copsle is set high, an interrupt is generated when the accepted path signal label changes. interrupts due to change of psl are masked when copsle is set low. pslme: the pslme bit enables the tributary path signal label mismatch interrupt for tributary tu #1 in tug2 #1 or tu3. when pslme is set high, an interrupt is generated when the accepted path signal label changes from mismatching the provisioned psl to matching the provisioned value, or vice versa. interrupts due to psl mismatch status change are masked when pslme is set low. pslue: the pslue bit enables the tributary path signal label unstable interrupt for tributary tu #1 in tug2 #1 or tu3. when pslue is set high, an interrupt is generated when the received path signal label becomes unstable or returns to stable. interrupts due to psl unstable status change are masked when pslue is set low. blkbip: the blkbip bit controls the accumulation of tributary bip-2 errors for the tributary tu #1 in tug2 #1 or the tu3 mapped into a tug3. when blkbip is set high, bip-2 errors are counted on a block basis; the bip error count is incremented by one when one or both of the bip-2 bits are in error. when blkbip is set low, bip-2 two errors are counted on a nibble basis; the bip error count is incremented once for each bip-2 bit that is in error. config[1:0]: the config[1:0] bits specify the tributary configuration of tributary group tug2 #1. the config[1:0] bits have no effect in tu3 mode. the configuration specified by the config[1:0] bits are selected as follows:
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 207 config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 208 register 101h, 201h, 301h: rtop, tu3 or tu #1 in tug2 #1, configuration and alarm status bit type function default bit 7 r/w rdiz7en 0 bit 6 r/w tupte 0 bit 5 r/w pdiven 0 bit 4 r psluv x bit 3 r pslmv x bit 2 r erdiv[2] x bit 1 r erdiv[1]/rfiv x bit 0 r erdiv[0]/rdiv x in tu3 mode, this register reports the alarm status of the tu3 mapped into a tug3. out of tu3 mode, this register reports alarm status and configures tu #1 in tug2 #1. rdiv: the rdiv bit indicates the remote defect indication status of tributary tu #1 in tug2 #1 or the tu3 mapped in a tug3 when rdiz7en is low. out of tu3 mode, rdiv is set high when the rdi bit in the v5 byte is set high for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers (addresses 0ch, 0dh, and 0eh). rdiv is set low when the rdi bit is set low for five or ten consecutive multiframes as determined by the rdi10 bit. in tu3 mode, rdiv is set high when the rdi bit in the g1 byte is set high for five or ten consecutive frames as determined by the rdi10 bit. rdiv is set low when the rdi bit is set low for five or ten consecutive frames as determined by the rdi10 bit. rfiv: the rfiv bit indicates the remote failure indication status of tributary tu #1 in tug2 #1 when rdiz7en is set low. rfiv is set high when the rfi bit in the
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 209 v5 byte is set high for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers (addresses 0ch, 0dh, and 0eh). rfiv is set low when the rfi bit is set low for five or ten consecutive multiframes as determined by the rdi10 bit. rfiv is not used when tu3 mode is enabled. erdiv[2:0]: the erdiv[2:0] bits indicates the extended remote defect indication status of tributary tu #1 in tug2 #1 or the tu3 mapped in a tug3 when rdiz7en is set high. the erdiv[2:0] bits are set to a new code when the same code in the extended rdi bits of the z7 byte or the g1 byte is seen for five or ten consecutive multiframes (frames in tu3 mode) as determined by the rdi10 bit in the rtop and rttb configuration registers (addresses 0ch, 0dh, and 0eh). pslmv: the pslmv bit indicates the path signal mismatch status of tributary tu #1 in tug2 #1 or tu3. pslmv is set high when the accepted psl differs from the provisioned value. pslmv is set low when the accepted psl has the same value as the provisioned one. psluv: the psluv bit indicates the path signal unstable status of tributary tu #1 in tug2 #1 or tu3. the psl unstable counter is incremented if the psl of the current multiframe differs from that in the previous multiframe. the counter is cleared to zero when the same psl is received for five consecutive multiframes. the tributary psl unstable alarm is asserted and psluv set high when the unstable counter reaches five. the psl unstable alarm is negated and psluv set low when the unstable counter is cleared. pdiven the pdiven bit controls the insertion of tributary path defect indication for tributary tu #1 in tug2 #1 or tu3 in the receive alarm port (rad). when pdiven is set high, pdi-v is asserted regardless of the state of the path signal label. when pdiven is set low, pdi-v is asserted if the incoming path signal label matches the pdi code in the pdi[2:0] bit of the corresponding rtop configuration register.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 210 tupte: the tupte bit determines the alarm conditions under which ais is inserted for tributary tu #1 in tug2 #1 or tu3 mapped in tug3. tupte is set high if tributary tu #1 or the tu3 is to be terminated in the network element containing this tupp+622 device. in this case, tributary ais is automatically inserted based on the contents of the global tributary alarm ais control register (address 10h). tupte is set low if tributary tu #1 or the tu3 is part of the through traffic in the network element containing this tupp+622 device. in this case, tributary ais is only inserted when a loss of pointer (lop) or a loss of multiframe (lom) alarm is detected (as determined by the global tributary alarm ais control register). rdiz7en: out of tu3 mode, the rdiz7en indicates which tributary path overhead byte is used for controlling the erdi[2:0] or rdi/rfi bits. when rdiz7en is set low, the rdi and rfi bits in the v5 byte are used to control the rdiv and rfiv register bits. when rdiz7en is set high, the three bit extended rdi code in the z7 byte is used to control the erdiv[2:0] register bits. in tu3 mode, the rdiz7en bit is used to control whether rdi or enhanced rdi is reported. when rdiz7en is set low, the rdi bit in the g1 byte is used to control the rdiv register bit. when rdiz7en is set high, the three bit extended rdi code in the g1 byte is used to control the erdiv[2:0] register bits.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 211 register 102h, 202h, 302h: rtop, tu3 or tu #1 in tug2 #1, expected path signal label bit type function default bit 7 r/w epsl[7] 0 bit 6 r/w epsl[6] 0 bit 5 r/w epsl[5] 0 bit 4 r/w epsl[4] 0 bit 3 r/w epsl[3] 0 bit 2 r/w epsl[2] 0 bit 1 r/w epsl[1] 0 bit 0 r/w epsl[0] 0 in tu3 mode (tu3 bit in vtpp configuration register set high), this register configures the expected path signal label of the tu3 mapped into a tug3 handled by the rtop. out of tu3 mode, this register configures the expected path signal label of tu #1 in tug2 #1. epsl[7:0]: in tu3 mode, the epsl[7:0] bits specifies the expected path signal label of the tu3 stream. out of tu3 mode, epsl[2:0] specifies the expected path signal label of tributary tu #1 in tug2 #1. the expected psl is compared with the accepted psl to determine the pslm state.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 212 register 103h, 203h, 303h: rtop, tu3 or tu #1 in tug2 #1, accepted path signal label bit type function default bit 7 r apsl[7] 0 bit 6 r apsl[6] 0 bit 5 r apsl[5] 0 bit 4 r apsl[4] 0 bit 3 r apsl[3] 0 bit 2 r apsl[2] 0 bit 1 r apsl[1] 0 bit 0 r apsl[0] 0 in tu3 mode (tu3 bit in vtpp configuration register set high), this register reports the accepted path signal label of the tu3 mapped into a tug3 handled by the rtop. out of tu3 mode, this register reports the accepted path signal label of tu #1 in tug2 #1. apsl[7:0]: in tu3 mode, the apsl[7:0] bits report the accepted path signal label of the tu3 stream. out of tu3 mode, apsl[2:0] specifies the accepted path signal label of tributary tu #1 in tug2 #1. the expected psl is compared with the accepted psl to determine the pslm state.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 213 register 104h, 204h, 304h: rtop, tu3 or tu #1 in tug2 #1, bip-2/bip-8 error count lsb bit type function default bit 7 r bip[7] x bit 6 r bip[6] x bit 5 r bip[5] x bit 4 r bip[4] x bit 3 r bip[3] x bit 2 r bip[2] x bit 1 r bip[1] x bit 0 r bip[0] x register 105h, 205h, 305h: rtop, tu3 or tu #1 in tug2 #1, bip-2/bip-8 error count msb bit type function default bit 7 r bip[15] x bit 6 r bip[14] x bit 5 r bip[13] x bit 4 r bip[12] x bit 3 r bip[11] x bit 2 r bip[10] x bit 1 r bip[9] x bit 0 r bip[8] x in tu3 mode (tu3 bit in vtpp configuration register set high), these registers report the number of block interleave parity (bip-8) errors detected in the tu3 mapped into a tug3 handled by the rtop. out of tu3 mode, this register reports the number of block interleave parity (bip-2) errors detected in tu #1 in tug2 #1. these registers do not saturate.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 214 bip[15:0]: the bip[15:0] bits report the number of tributary path bit-interleaved parity errors that have been detected since the last time the bip-2/bip-8 registers were polled. the bip-2/bip-8 registers are polled by writing to the input signal activity, accumulate trigger register. the write access transfers the internally accumulated error count to the bip-2/bip-8 registers within 10 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. bip-2/bip-8 errors may be accumulated on a nibble/bit basis or block basis as controlled by the blkbip register bit. in tu3 mode, all bip[15:0] are valid. out of tu3 mode, only bip[10:0] are valid, bip[15:11] are held low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 215 register 106h, 206h, 306h: rtop, tu3 or tu #1 in tug2 #1, rei error count lsb bit type function default bit 7 r rei[7] x bit 6 r rei[6] x bit 5 r rei[5] x bit 4 r rei[4] x bit 3 r rei[3] x bit 2 r rei[2] x bit 1 r rei[1] x bit 0 r rei[0] x register 107h, 207h, 307h: rtop, tu3 or tu #1 in tug2 #1, rei error count msb bit type function default bit 7 r rei[15] x bit 6 r rei[14] x bit 5 r rei[13] x bit 4 r rei[12] x bit 3 r rei[11] x bit 2 r rei[10] x bit 1 r rei[9] x bit 0 r rei[8] x in tu3 mode (tu3 bit in vtpp configuration register set high), these registers report the number of remote error indications (rei) detected in the tu3 mapped into a tug3 handled by the rtop. out of tu3 mode, this register reports the number of remote error indications (rei) detected in tu #1 in tug2 #1.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 216 rei[15:0]: the rei[15:0] bits report the number of tributary path remote error indications that have been detected since the last time the rei registers were polled. the rei registers are polled by writing to the input signal activity, accumulate trigger register. the write access transfers the internally accumulated error counts to the rei registers within 10 s and simultaneously resets the internal counter to begin a new cycle of error accumulation.in tu3 mode, all rei[15:0] are valid. out of tu3 mode, only rei[10:0] are valid, rei[15:11] are held low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 217 register 108h, 110h, 118h, 120h, 128h, 130h: register 208h, 210h, 218h, 220h, 228h, 230h: register 308h, 310h, 318h, 320h, 328h, 330h: rtop, tu #1 in tug2 #2 to tug2 #7, configuration bit type function default bit 7 r/w config[1] 1 bit 6 r/w config[0] 1 bit 5 r/w blkbip 0 bit 4 r/w pslue 0 bit 3 r/w pslme 0 bit 2 r/w copsle 0 bit 1 r/w rfie 0 bit 0 r/w rdie 0 this set of registers configures the operational modes of tu #1 in tug2 #2 to tug2 #7. these registers have no effect in tu3 mode. rdie: the rdie bit enables the remote defect indication interrupt for tributary tu #1 in the corresponding tug2. when rdie is set high, an interrupt is generated upon changes of rdi status. interrupts due to rdi status change are masked when rdie is set low. the rdi status is derived from bit 8 of the v5 byte when rdiz7en is set low and from bits 5 to 7 of the z7 byte when rdiz7en is set high. rfie: the rfie bit enables the remote failure indication interrupt for tributary tu #1 in the correspondiing tug2. when rdiz7en is set low, an interrupt is generated upon assertion and negation events of the rfiv bit when rfie is set high. interrupts due to rfiv status change are masked when rfie is set low. when rdiz7en is set high, rfie is ignored. the rfie bit is not used when the rtop is in tu3 mode is enabled.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 218 copsle: the copsle bit enables the change of tributary path signal label interrupt for tributary tu #1 in the corresponding tug2. when copsle is set high, an interrupt is generated when the accepted path signal label changes. interrupts due to change of psl are masked when copsle is set low. pslme: the pslme bit enables the tributary path signal label mismatch interrupt for tributary tu #1 in the corresponding tug2. when pslme is set high, an interrupt is generated when the accepted path signal label changes from mismatching the provisioned psl to matching the provisioned value, or vice versa. interrupts due to psl mismatch status change are masked when pslme is set low. pslue: the pslue bit enables the tributary path signal label unstable interrupt for tributary tu #1 in the corresponding tug2. when pslue is set high, an interrupt is generated when the received path signal label becomes unstable or returns to stable. interrupts due to psl unstable status change are masked when pslue is set low. blkbip: the blkbip bit controls the accumulation of tributary bip-2 errors for the tributary tu #1 in the corresponding tug2. when blkbip is set high, bip-2 errors are counted on a block basis; the bip error count is incremented by one when one or both of the bip-2 bits are in error. when blkbip is set low, the bip error count is incremented once for each bip-2 bit that is in error. config[1:0]: the config[1:0] bits specify the tributary configuration of the corresponding tug2. the configuration specified by the config[1:0] bits are selected as follows:
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 219 config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 220 register 109h, 111h, 119h, 121h, 129h, 131h: register 209h, 211h, 219h, 221h, 229h, 231h: register 309h, 311h, 319h, 321h, 329h, 331h: rtop, tu #1 in tug2 #2 to tug2 #7, configuration and alarm status bit type function default bit 7 r/w rdiz7en 0 bit 6 r/w tupte 0 bit 5 r/w pdiven 0 bit 4 r psluv x bit 3 r pslmv x bit 2 r/w erdiv[2] 0 bit 1 r erdiv[1]/rfiv x bit 0 r erdiv[0]/rdiv x this set of registers reports alarm status and configures tu #1 in tug2 #2 to tug2 #7. these registers have no effect in tu3 mode. rdiv: the rdiv bit indicates the remote defect indication status of tributary tu #1 in the corresponding tug2 when rdiz7en is low. rdiv is set high when the rdi bit in the v5 byte is set high for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers (addresses 0ch, 0dh, and 0eh). rdiv is set low when the rdi bit is set low for five or ten consecutive multiframes as determined by the rdi10 bit rfiv: the rfiv bit indicates the remote failure indication status of tributary tu #1 in the corresponding tug2 when rdiz7en is set low. rfiv is set high when the rfi bit in the v5 byte is set high for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers (addresses 0ch, 0dh, and 0eh). rfiv is set low when the rfi bit is set low for five or ten consecutive multiframes as determined by the rdi10 bit.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 221 erdiv[2:0]: the erdiv[2:0] bits indicates the extended remote defect indication status of tributary tu #1 in the corresponding tug2 when rdiz7en is set high. the erdiv[2:0] bits are set to a new code when the same code in the extended rdi bits of the z7 byte is seen for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers (addresses 0ch, 0dh, and 0eh). pslmv: the pslmv bit indicates the path signal mismatch status of tributary tu #1 in the corresponding tug2. pslmv is set high when the accepted psl differs from the provisioned value. pslmv is set low when the accepted psl has the same value as the provisioned one. psluv: the psluv bit indicates the path signal unstable status of tributary tu #1 in the corresponding tug2. the psl unstable counter is incremented if the psl of the current multiframe differs form that in the previous multiframe. the counter is cleared to zero when the same psl is received for five consecutive multiframes. the tributary psl unstable alarm is asserted and psluv set high when the unstable counter reaches five. the psl unstable alarm is negated and psluv set low when the unstable counter is cleared. pdiven: the pdiven bit modifies the payload defect indication status pdiv of tributary tu #1 in the corresponding tug2 . the pdiv output is set high when the psl in the v5 byte is set to the bit pattern specified by the pdicode[2:0] register bits for five consecutive multiframes. the pdiv output is set low when the psl is set to any other bit pattern for five consecutive multiframes. when pdiven is set high, the pdiv output is permanently set high independent of the tributary's defect status until the pdiven is set low. tupte: the tupte bit determines the alarm conditions under which ais is inserted for tributary tu #1 in the corresponding tug2. tupte is set high if tributary tu #1 is to be terminated in the network element containing this tupp+622 device. in this case, tributary ais is automatically inserted based on the contents of the global tributary alarm ais control register (address 10h).
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 222 tupte is set low if tributary tu #1 is part of the through traffic in the network element containing this tupp+622 device. in this case, tributary ais is only inserted when a loss of pointer (lop) or a loss of multiframe (lom) alarm is detected (as determined by the global tributary alarm ais control register). rdiz7en: the rdiz7en indicates which tributary path overhead byte is used for controlling the erdi[2:0] or rdi/rfi bits of tributary tu #1 in the corresponding tug2 . when rdiz7en is set low, the rdi and rfi bits in the v5 byte are used to control the rdiv and rfiv register bits. when rdiz7en is set high, the three bit extended rdi code in the z7 byte is used to control the erdiv[2:0] register bits.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 223 register 10ah, 112h, 11ah, 122h, 12ah, 132h: register 20ah, 212h, 21ah, 222h, 22ah, 232h: register 30ah, 312h, 31ah, 322h, 32ah, 332h: rtop, tu #1 in tug2 #2 to tug2 #7, expected path signal label bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w epsl[2] 0 bit 1 r/w epsl[1] 0 bit 0 r/w epsl[0] 0 this set of registers configures the expected path signal label of tu #1 in tug2 #2 to tug2 #7. these registers have no effect in tu3 mode. epsl[2:0]: the epsl[2:0] bits specifies the expected path signal label of tributary tu #1 in the corresponding tug2. the expected psl is compared with the accepted psl to determine the pslm state.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 224 register 10bh, 113h, 11bh, 123h, 12bh, 133h: register 20bh, 213h, 21bh, 223h, 22bh, 233h: register 30bh, 313h, 31bh, 323h, 32bh, 333h: rtop, tu #1 in tug2 #2 to tug2 #7, accepted path signal label bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r apsl[2] 0 bit 1 r apsl[1] 0 bit 0 r apsl[0] 0 this set of registers reports the accepted path signal label of tu #1 in tug2 #2 to tug2 #7. these registers have no effect in tu3 mode. apsl[2:0]: the apsl[2:0] bits report the accepted path signal label of tributary tu #1 in the corresponding tug2. an incoming psl is accepted when the same value is received for five consecutive multiframes.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 225 register 10ch, 114h, 11ch, 124h, 12ch, 134h: register 20ch, 214h, 21ch, 224h, 22ch, 234h: register 30ch, 314h, 31ch, 324h, 32ch, 334h: rtop, tu #1 in tug2 #2 to tug2 #7, bip-2 error count lsb bit type function default bit 7 r bip[7] x bit 6 r bip[6] x bit 5 r bip[5] x bit 4 r bip[4] x bit 3 r bip[3] x bit 2 r bip[2] x bit 1 r bip[1] x bit 0 r bip[0] x register 10dh, 115h, 11dh, 125h, 12dh, 135h: register 20dh, 215h, 21dh, 225h, 22dh, 235h: register 30dh, 315h, 31dh, 325h, 32dh, 335h: rtop, tu #1 in tug2 #2 to tug2 #7, bip-2 error count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r bip[10] x bit 1 r bip[9] x bit 0 r bip[8] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 226 these sets of registers report the number of block interleave parity (bip-2) errors detected in tu #1 in tug2 #2 to tug2 #7 in the previous accumulation interval. these registers have no effect in tu3 mode. these registers do not saturate. bip[10:0]: the bip[10:0] bits report the number of tributary path bit-interleaved parity errors that have been detected since the last time the bip-2 registers were polled. the bip-2 registers are polled by writing to any of the input signal activity monitor, accumulate trigger register. the write access transfers the internally accumulated error count to the bip-2 registers within 10 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. bip-2 errors may be accumulated on a nibble basis or block basis as controlled by the blkbip register bit.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 227 register 10eh, 116h, 11eh, 126h, 12eh, 136h: register 20eh, 216h, 21eh, 226h, 22eh, 236h: register 30eh, 316h, 31eh, 326h, 32eh, 336h: tu #1 in tug2 #2 to tug2 #7, rei error count lsb bit type function default bit 7 r rei[7] x bit 6 r rei[6] x bit 5 r rei[5] x bit 4 r rei[4] x bit 3 r rei[3] x bit 2 r rei[2] x bit 1 r rei[1] x bit 0 r rei[0] x register 10fh, 117h, 11fh, 127h, 12fh, 137h: register 20fh, 217h, 21fh, 227h, 22fh, 237h: register 30fh, 317h, 31fh, 327h, 32fh, 337h: tu #1 in tug2 #2 to tug2 #7, rei error count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r rei[10] x bit 1 r rei[9] x bit 0 r rei[8] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 228 these registers report the number of remote error indications (rei) detected in tu #1 in tug2 #2 to tug2 #7 in the previous accumulation interval. these registers have no effect in tu3 mode. rei[10:0]: the rei[10:0] bits report the number of tributary path remote error indications that have been detected since the last time the rei registers were polled. the rei registers are polled by applying by writing to the input signal activity monitor, accumulate trigger register. the write access transfers the internally accumulated error count to the rei registers within 10 s and simultaneously resets the internal counter to begin a new cycle of error accumulation.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 229 register 138h, 238h, 338h: rtop, tu3 or tu #1 in tug2 #1 to tug2 #7, copsl interrupt bit type function default bit 7 r/w reserved 0 bit 6 r copsl7i 0 bit 5 r copsl6i 0 bit 4 r copsl5i 0 bit 3 r copsl4i 0 bit 2 r copsl3i 0 bit 1 r copsl2i 0 bit 0 r copsl1i 0 this register is used to identify and acknowledge change of path signal label interrupts for the tributaries tu #1 in tug2 #1 to tug2 #7. it is also used to identify and acknowledge tu3 change of path signal label interrupts. copsl1i: the copsl1i bit identifies the source of change of path signal label interrupts. in tu3 mode, the copsl1i bit reports and acknowledges copsl interrupts of the tu3 stream. out of tu3 mode, the copsl1i bit reports and acknowledges copsl interrupt of tu #1 in tug2 #1. interrupts are generated when the accepted psl changes. the copsl1i bit is set high when a change of psl event occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. copsl1i remains valid when interrupts are not enabled (copsle set low) and may be polled to detect change of path signal label events. copsl2i-copsl7i: the copsl2i to copsl7i bits identify the source of change of path signal label interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. out of tu3 mode, copsl2i to copsl7i bits report and acknowledge copsl interrupt of tu #1 in tug2 #2 to tug2 #7, respectively. interrupts are generated when the accepted psl changes. an copsl x i bit is
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 230 set high when a change of psl event on the associated tributary (tu #1 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. copsl x i remains valid when interrupts are not enabled (copsle set low) and may be polled to detect change of path signal label events. reserved: the reserved bit must be written with a logic 0 for proper operation of the tupp+622.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 231 register 139h, 239h, 339h: rtop, tu3 or tu #1 in tug2 #1 to tug2 #7, pslm interrupt bit type function default bit 7 unused x bit 6 r pslm7i 0 bit 5 r pslm6i 0 bit 4 r pslm5i 0 bit 3 r pslm4i 0 bit 2 r pslm3i 0 bit 1 r pslm2i 0 bit 0 r pslm1i 0 this register is used to identify and acknowledge path signal label mismatch interrupts for the tributaries tu #1 in tug2 #1 to tug2 #7. it is also used to identify and acknowledge tu3 path signal label mismatch interrupts. pslm1i: the pslm1i bit identifies the source of path signal label mismatch interrupts. in tu3 mode, the pslm1i bit reports and acknowledges pslm interrupts of the tu3 stream. out of tu3 mode, the pslm1i bit reports and acknowledges pslm interrupt of tu #1 in tug2 #1. interrupts are generated when the accepted psl becomes matched to the expected psl or becomes mismatched to the expected psl. the pslm1i bit is set high when a change of in the psl matched state occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pslm1i remains valid when interrupts are not enabled (pslme set low) and may be polled to detect path signal label match/mismatch events. pslm1i-pslm7i: the pslm1i to pslm7i bits identify the source of path signal label mismatch interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. out of tu3 mode, pslm2i to pslm7i bits report and acknowledge pslm interrupt of tu #1 in tug2 #2 to tug2 #7, respectively. interrupts are
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 232 generated when the accepted psl becomes matched to the expected psl or becomes mismatched to the expected psl. an pslm x i bit is set high when a change of psl matched state on the associated tributary (tu #1 in tug2 # x ) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pslm x i remains valid when interrupts are not enabled (pslme set low) and may be polled to detect path signal label match/mismatch events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 233 register 13ah, 23ah, 33ah: rtop, tu3 or tu #1 in tug2 #1 to tug2 #7, pslu interrupt bit type function default bit 7 unused x bit 6 r pslu7i 0 bit 5 r pslu6i 0 bit 4 r pslu5i 0 bit 3 r pslu4i 0 bit 2 r pslu3i 0 bit 1 r pslu2i 0 bit 0 r pslu1i 0 this register is used to identify and acknowledge path signal label unstable interrupts for the tributaries tu #1 in tug2 #1 to tug2 #7. it is also used to identify and acknowledge tu3 path signal label unstable interrupts. pslu1i: the pslu1i bit identifies the source of path signal label unstable interrupts. in tu3 mode, the pslu1i bit reports and acknowledges pslu interrupts of the tu3 stream. out of tu3 mode, the pslu1i bit reports and acknowledges pslu interrupt of tu #1 in tug2 #1. interrupts are generated when the received psl becomes unstable or returns to stable. the pslu1i bit is set high when a change of in the psl unstable state occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pslu1i remains valid when interrupts are not enabled (pslue set low) and may be polled to detect path signal label stable/unstable events. pslu2i-pslu7i: the pslu2i to pslu7i bits identify the source of path signal label mismatch interrupts. pslu2i to pslu7i bits report and acknowledge pslu interrupt of tu #1 in tug2 #2 to tug2 #7, respectively. interrupts are generated when the received psl becomes unstable or returns to stable. an pslu x i bit is set
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 234 high when a change of psl unstable state on the associated tributary (tu #1 in tug2 # x ) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pslu x i remains valid when interrupts are not enabled (pslue set low) and may be polled to detect path signal label stable/unstable events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 235 register 13bh, 23bh, 33bh: rtop, tu3 or tu #1 in tug2 #1 to tug2 #7, rdi interrupt bit type function default bit 7 unused x bit 6 r rdi7i 0 bit 5 r rdi6i 0 bit 4 r rdi5i 0 bit 3 r rdi4i 0 bit 2 r rdi3i 0 bit 1 r rdi2i 0 bit 0 r rdi1i 0 this register is used to identify and acknowledge remote defect indication interrupts for the tributaries tu #1 in tug2 #1 to tug2 #7. it is also used to identify and acknowledge tu3 remote defect indication interrupts. rdi1i: the rdi1i bit identify the source of remote defect indication interrupts. in tu3 mode, the rdi1i bit reports and acknowledges rdi interrupt of the tu3 stream. out of tu3 mode, the rdi1i bit reports and acknowledges rdi interrupt of tu #1 in tug2 #1. interrupts are generated when the received rdi state changes. the rdi1i bit is set high when a change of rdi state event occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. rdi1i remains valid when interrupts are not enabled (rdie set low) and may be polled to detect change of remote defect indication events. rdi2i-rdi7i: the rdi2i to rdi7i bits identify the source of remote defect indication interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. out of tu3 mode, the rdi2i to rdi7i bits report and acknowledge rdi interrupt of tu #1 in tug2 #2 to tug2 #7, respectively. interrupts are generated when the received rdi state changes. an rdi x i bit is set high
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 236 when a change of rdi state on the associated tributary (tu #1 in tug2 # x ) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. rdi x i remains valid when interrupts are not enabled (rdie set low) and may be polled to detect change of remote defect indication events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 237 register 13ch, 23ch, 33ch: rtop, tu3 auxiliary rdi interrupt or tu #1 in tug2 #1 to tug2 #7 rfi interrupt bit type function default bit 7 unused x bit 6 r rfi7i 0 bit 5 r rfi6i 0 bit 4 r rfi5i 0 bit 3 r rfi4i 0 bit 2 r rfi3i 0 bit 1 r rfi2i 0 bit 0 r rfi1i 0 this register is used to identify and acknowledge remote failure indication interrupts for the tributaries tu #1 in tug2 #1 to tug2 #7. it is also used to identify and acknowledge tu3 auxiliary remote defect indication interrupts. rfi1i: the rfi1i bit identify the source of remote defect indication interrupts. in tu3 mode, the rfi1i bit reports and acknowledges auxiliary rdi interrupt of the tu3 stream. out of tu3 mode, the rfi1i bit reports and acknowledges rfi interrupt of tu #1 in tug2 #1. interrupts are generated when the received rfi state changes. the rfi1i bit is set high when a change of rdi state event occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. rfi1i remains valid when interrupts are not enabled (rfie set low) and may be polled to detect change of remote defect indication events. rfi2i-rfi7i: the rfi2i to rfi7i bits identify the source of remote failure indication interrupts. rfi1i to rfi7i bits report and acknowledge rfi interrupt of tu #1 in tug2 #2 to tug2 #7, respectively. interrupts are generated when the received rfi state changes. an rfi x i bit is set high when a change of rfi state on the associated tributary (tu #1 in tug2 # x ) occurs and are cleared
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 238 immediately following a read of this register, which also acknowledges and clears the interrupt. rfi x i remains valid when interrupts are not enabled (rfie set low) and may be polled to detect change of remote failure indication events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 239 register 13dh, 23dh, 33dh: rtop, tu #1 in tug2 #1 to tug2 #7, in band error reporting configuration bit type function default bit 7 unused x bit 6 r/w iber7 0 bit 5 r/w iber6 0 bit 4 r/w iber5 0 bit 3 r/w iber4 0 bit 2 r/w iber3 0 bit 1 r/w iber2 0 bit 0 r/w iber1 0 this register enables the inband error reporting mode of the tributaries tu #1 in tug2 #1 to tug2 #7. iber1-iber7: the iber1 to iber7 bits control in band error reporting for tributary tu #1 in tug2 #1 to tug2 #7, respectively. setting an iber x bit high causes in band error reporting information to be inserted in the v5 byte of tributary tu #1 of the corresponding tug2. when an iber x bit is low, in band error reporting is disabled and the v5 byte of tributary tu #1 of the corresponding tug2 is not modified.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 240 register 13eh, 23eh, 33eh: rtop, tu3 or tu #1 in tug2 #1 to tug2 #7, controllable output configuration bit type function default bit 7 unused x bit 6 r/w cout7 0 bit 5 r/w cout6 0 bit 4 r/w cout5 0 bit 3 r/w cout4 0 bit 2 r/w cout3 0 bit 1 r/w cout2 0 bit 0 r/w cout1 0 this register controls the configurable output (cout) output for the tributaries tu #1 in tug2 #1 to tug2 #7 and cout output for the tu3 mode. cout1: the cout1 bit controls the cout output for tributary tu #1 in tug2 #1 or tu3 in a tug3. in tu3 mode, setting the cout1 high will cause the cout output to be set high when the incoming data stream is part of the tu3 in a tug3. in non-tu3 modes, setting the cout1 high will cause the cout output to be high when the incoming data stream is part of tributary tu #1 in tug2 #1. when cout1 is set low, the cout output will be low when the incoming data stream is part of tributary tu #1 in tug2 #1 or a tu3 in a tug3. cout2-cout7: the cout2 to cout7 bits control the cout output for tributary tu #1 in tug2 #2 to tug2 #7, respectively. setting a cout x bit high will force the cout output to be high when the incoming data stream is part of tributary tu #1 of the corresponding tug2. when an cout x bit is low, the cout output will be low when the incoming data stream is part of tributary tu #1 of the corresponding tug2.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 241 register 140h, 148h, 150h, 158h, 160h, 168h, 170h: register 240h, 248h, 250h, 258h, 260h, 268h, 270h: register 340h, 348h, 350h, 358h, 360h, 368h, 370h: rtop, tu #2 in tug2 #1 to tug2 #7, configuration bit type function default bit 7 r config[1] 1 bit 6 r config[0] 1 bit 5 r/w blkbip 0 bit 4 r/w pslue 0 bit 3 r/w pslme 0 bit 2 r/w copsle 0 bit 1 r/w rfie 0 bit 0 r/w rdie 0 this set of registers configures the operational modes of tu #2 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) mode, the associated register in this set has no effect. rdie: the rdie bit enables the remote defect indication interrupt for tributary tu #1 in the corresponding tug2. when rdie is set high, an interrupt is generated upon changes of rdi status. interrupts due to rdi status change are masked when rdie is set low. the rdi status is derived from bit 8 of the v5 byte when rdiz7en is set low and from bits 5 to 7 of the z7 byte when rdiz7en is set high. rfie: the rfie bit enables the remote failure indication interrupt for tributary tu #1 in the corresponding tug2. when rdiz7en is set low, an interrupt is generated upon assertion and negation events of the rfiv bit when rfie is set high. interrupts due to rfiv status change are masked when rfie is set
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 242 low. when rdiz7en is set high, rfie is ignored. the rfie bit is not used when the rtop is in tu3 mode is enabled. copsle: the copsle bit enables the change of tributary path signal label interrupt for tributary tu #2 in the corresponding tug2. when copsle is set high, an interrupt is generated when the accepted path signal label changes. interrupts due to change of psl are masked when copsle is set low. pslme: the pslme bit enables the tributary path signal label mismatch interrupt for tributary tu #2 in the corresponding tug2. when pslme is set high, an interrupt is generated when the accepted path signal label changes from mismatching the provisioned psl to matching the provisioned value, or vice versa. interrupts due to psl mismatch status change are masked when pslme is set low. pslue: the pslue bit enables the tributary path signal label unstable interrupt for tributary tu #2 in the corresponding tug2. when pslue is set high, an interrupt is generated when the received path signal label becomes unstable or returns to stable. interrupts due to psl unstable status change are masked when pslue is set low. blkbip: the blkbip bit controls the accumulation of tributary bip-2 errors for the tributary tu #2 in the corresponding tug2. when blkbip is set high, bip-2 errors are counted on a block basis; the bip error count is incremented by one when one or both of the bip-2 bits are in error. when blkbip is set low, the bip error count is incremented once for each bip-2 bit that is in error. config[1:0]: the config[1:0] bits specify the tributary configuration of the corresponding tug2. the configuration specified by the config[1:0] bits are selected as follows:
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 243 config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 244 register 141h, 149h, 151h, 159h, 161h, 169h, 171h: register 241h, 249h, 251h, 259h, 261h, 269h, 271h: register 341h, 349h, 351h, 359h, 361h, 369h, 371h: rtop, tu #2 in tug2 #1 to tug2 #7, configuration and alarm status bit type function default bit 7 r/w rdiz7en 0 bit 6 r/w tupte 0 bit 5 r/w pdiven 0 bit 4 r psluv x bit 3 r pslmv x bit 2 r erdiv[2] x bit 1 r erdiv[1]/rfiv x bit 0 r erdiv[0]/rdiv x this set of registers reports alarm status and configures tu #2 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) mode, the associated register in this set has no effect. rdiv: the rdiv bit indicates the remote defect indication status of tributary tu #2 in the corresponding tug2 when rdiz7en is low. rdiv is set high when the rdi bit in the v5 byte is set high for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers (addresses 0ch, 0dh, and 0eh). rdiv is set low when the rdi bit is set low for five or ten consecutive multiframes as determined by the rdi10 bit rfiv: the rfiv bit indicates the remote failure indication status of tributary tu #2 in the corresponding tug2 when rdiz7en is set low. rfiv is set high when the rfi bit in the v5 byte is set high for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 245 (addresses 0ch, 0dh, and 0eh). rfiv is set low when the rfi bit is set low for five or ten consecutive multiframes as determined by the rdi10 bit. erdiv[2:0]: the erdiv[2:0] bits indicates the extended remote defect indication status of tributary tu #2 in the corresponding tug2 when rdiz7en is set high. the erdiv[2:0] bits are set to a new code when the same code in the extended rdi bits of the z7 byte is seen for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers (addresses 0ch, 0dh, and 0eh). pslmv: the pslmv bit indicates the path signal mismatch status of tributary tu #2 in the corresponding tug2. pslmv is set high when the accepted psl differs from the provisioned value. pslmv is set low when the accepted psl has the same value as the provisioned one. psluv: the psluv bit indicates the path signal unstable status of tributary tu #2 in the corresponding tug2. the psl unstable counter is incremented if the psl of the current multiframe differs form that in the previous multiframe. the counter is cleared to zero when the same psl is received for five consecutive multiframes. the tributary psl unstable alarm is asserted and psluv set high when the unstable counter reaches five. the psl unstable alarm is negated and psluv set low when the unstable counter is cleared. pdiven: the pdiven bit modifies the payload defect indication status pdiv of tributary tu #2 in the corresponding tug2 . the pdiv output is set high when the psl in the v5 byte is set to the bit pattern specified by the pdicode[2:0] input for five consecutive multiframes. the pdiv output is set low when the psl is set to any other bit pattern for five consecutive multiframes. when pdiven is set high, the pdiv output is permanently set high independent of the tributary's defect status until the pdiven is set low. tupte: the tupte bit determines the alarm conditions under which ais is inserted for tributary tu #2 in the corresponding tug2. tupte is set high if tributary
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 246 tu #2 is to be terminated in the network element containing this tupp+622 device. in this case, tributary ais is automatically inserted based on the contents of the global tributary alarm ais control register (address 10h). tupte is set low if tributary tu #2 is part of the through traffic in the network element containing this tupp+622 device. in this case, tributary ais is only inserted when a loss of pointer (lop) or a loss of multiframe (lom) alarm is detected (as determined by the global tributary alarm ais control register). rdiz7en: the rdiz7en indicates which tributary path overhead byte is used for controlling the erdi[2:0] or rdi/rfi bits of tributary tu #2 in the corresponding tug2 . when rdiz7en is set low, the rdi and rfi bits in the v5 byte are used to control the rdiv and rfiv register bits. when rdiz7en is set high, the three bit extended rdi code in the z7 byte is used to control the erdiv[2:0] register bits.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 247 register 142h, 14ah, 152h, 15ah, 162h, 16ah, 172h: register 242h, 24ah, 252h, 25ah, 262h, 26ah, 272h: register 342h, 34ah, 352h, 35ah, 362h, 36ah, 372h: rtop, tu #2 in tug2 #1 to tug2 #7, expected path signal label bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w epsl[2] 0 bit 1 r/w epsl[1] 0 bit 0 r/w epsl[0] 0 this set of registers configures the expected path signal label of tu #2 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) mode, the associated register in this set has no effect. epsl[2:0]: the epsl[2:0] bits specifies the expected path signal label of tributary tu #2 in the corresponding tug2. the expected psl is compared with the accepted psl to determine the pslm state.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 248 register 143h, 14bh, 153h, 15bh, 163h, 16bh, 173h: register 243h, 24bh, 253h, 25bh, 263h, 26bh, 273h: register 343h, 34bh, 353h, 35bh, 363h, 36bh, 373h: rtop, tu #2 in tug2 #1 to tug2 #7, accepted path signal label bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r apsl[2] 0 bit 1 r apsl[1] 0 bit 0 r apsl[0] 0 this set of registers reports the accepted path signal label of tu #2 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) mode, the associated register in this set has no effect. apsl[2:0]: the apsl[2:0] bits report the accepted path signal label of tributary tu #2 in tug2 #1 to tug2 #7. an incoming psl is accepted when the same value is received for five consecutive multiframes.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 249 register 144h, 14ch, 154h, 15ch, 164h, 16ch, 174h: register 244h, 24ch, 254h, 25ch, 264h, 26ch, 274h: register 344h, 34ch, 354h, 35ch, 364h, 36ch, 374h: rtop, tu #2 in tug2 #1 to tug2 #7, bip-2 error count lsb bit type function default bit 7 r bip[7] x bit 6 r bip[6] x bit 5 r bip[5] x bit 4 r bip[4] x bit 3 r bip[3] x bit 2 r bip[2] x bit 1 r bip[1] x bit 0 r bip[0] x register 145h, 14dh, 155h, 15dh, 165h, 16dh, 175h: register 245h, 24dh, 255h, 25dh, 265h, 26dh, 275h: register 345h, 34dh, 355h, 35dh, 365h, 36dh, 375h: rtop, tu #2 in tug2 #1 to tug2 #7, bip-2 error count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r bip[10] x bit 1 r bip[9] x bit 0 r bip[8] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 250 these registers report the number of block interleave parity (bip-2) errors detected in tu #2 in tug2 #1 to tug2 #7 in the previous accumulation interval. these registers contain invalid data in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) mode, the data in associated registers are invalid. these registers do not saturate. bip[10:0]: the bip[10:0] bits report the number of tributary path bit-interleaved parity errors that have been detected since the last time the bip-2 registers were polled. the bip-2 registers are polled by writing to the input signal activity monitor, accumulate trigger register. the write access transfers the internally accumulated error count to the bip-2 registers within 10 s and resets the internal counter simultaneously to begin a new cycle of error accumulation.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 251 register 146h, 14eh, 156h, 15eh, 166h, 16eh, 176h: register 246h, 24eh, 256h, 25eh, 266h, 26eh, 276h: register 346h, 34eh, 356h, 35eh, 366h, 36eh, 376h: rtop, tu #2 in tug2 #1 to tug2 #7, rei error count lsb bit type function default bit 7 r rei[7] x bit 6 r rei[6] x bit 5 r rei[5] x bit 4 r rei[4] x bit 3 r rei[3] x bit 2 r rei[2] x bit 1 r rei[1] x bit 0 r rei[0] x register 147h, 14fh, 157h, 15fh, 167h, 16fh, 177h: register 247h, 24fh, 257h, 25fh, 267h, 26fh, 277h: register 347h, 34fh, 357h, 35fh, 367h, 36fh, 377h: rtop, tu #2 in tug2 #1 to tug2 #7, rei error count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r rei[10] x bit 1 r rei[9] x bit 0 r rei[8] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 252 these registers report the number of remote error indications (rei) detected in tu #2 in tug2 #1 to tug2 #7 in the previous accumulation interval. these registers contain invalid data in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) mode, the associated registers in this set contain invalid data. rei[10:0]: the rei[10:0] bits report the number of tributary path remote error indications that have been detected since the last time the rei registers were polled. the rei registers are polled by writing to the input signal activity monitor, accumulate trigger registers. the write access transfers the internally accumulated error count to the rei registers within 10 s and resets the internal counter simultaneoulsy to begin a new cycle of error accumulation.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 253 register 178h, 278h, 378h: rtop, tu #2 in tug2 #1 to tug2 #7, copsl interrupt bit type function default bit 7 unused x bit 6 r copsl7i 0 bit 5 r copsl6i 0 bit 4 r copsl5i 0 bit 3 r copsl4i 0 bit 2 r copsl3i 0 bit 1 r copsl2i 0 bit 0 r copsl1i 0 this register is used to identify and acknowledge change of path signal label interrupts for the tributaries tu #2 in tug2 #1 to tug2 #7. copsl1i-copsl7i: the copsl1i to copsl7i bits identify the source of change of path signal label interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) mode, the associated copsl x i bit is unused and will return a logic 0 when read. when operational, the copsl1i to copsl7i bits report and acknowledge copsl interrupt of tu #2 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the accepted psl changes. an copsl x i bit is set high when a change of psl event on the associated tributary (tu #2 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. copsl x i remains valid when interrupts are not enabled (copsle set low) and may be polled to detect change of path signal label events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 254 register 179h, 279h, 379h: rtop, tu #2 in tug2 #1 to tug2 #7, pslm interrupt bit type function default bit 7 unused x bit 6 r pslm7i 0 bit 5 r pslm6i 0 bit 4 r pslm5i 0 bit 3 r pslm4i 0 bit 2 r pslm3i 0 bit 1 r pslm2i 0 bit 0 r pslm1i 0 this register is used to identify and acknowledge path signal label mismatch interrupts for the tributaries tu #2 in tug2 #1 to tug2 #7. pslm1i-pslm7i: the pslm1i to pslm7i bits identify the source of path signal label mismatch interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) mode, the associated pslm x i bit is unused and will return a logic 0 when read. when operational, the pslm1i to pslm7i bits report and acknowledge pslm interrupt of tu #2 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the accepted psl becomes matched to the expected psl or becomes mismatched to the expected psl. an pslm x i bit is set high when a change of psl matched state on the associated tributary (tu #2 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pslm x i remains valid when interrupts are not enabled (pslme set low) and may be polled to detect path signal label match/mismatch events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 255 register 17ah, 27ah, 37ah: rtop, tu #2 in tug2 #1 to tug2 #7, pslu interrupt bit type function default bit 7 unused x bit 6 r pslu7i 0 bit 5 r pslu6i 0 bit 4 r pslu5i 0 bit 3 r pslu4i 0 bit 2 r pslu3i 0 bit 1 r pslu2i 0 bit 0 r pslu1i 0 this register is used to identify and acknowledge path signal label unstable interrupts for the tributaries tu #2 in tug2 #1 to tug2 #7. pslu1i-pslu7i: the pslu1i to pslu7i bits identify the source of path signal label mismatch interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) mode, the associated pslu x i bit is unused and will return a logic 0 when read. when operational, the pslu1i to pslu7i bits report and acknowledge pslu interrupt of tu #2 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the received psl becomes unstable or returns to stable. an pslu x i bit is set high when a change of psl unstable state on the associated tributary (tu #2 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pslu x i remains valid when interrupts are not enabled (pslue set low) and may be polled to detect path signal label stable/unstable events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 256 register 17bh, 27bh, 37bh: rtop, tu #2 in tug2 #1 to tug2 #7, rdi interrupt bit type function default bit 7 unused x bit 6 r rdi7i 0 bit 5 r rdi6i 0 bit 4 r rdi5i 0 bit 3 r rdi4i 0 bit 2 r rdi3i 0 bit 1 r rdi2i 0 bit 0 r rdi1i 0 this register is used to identify and acknowledge remote defect indication interrupts for the tributaries tu #2 in tug2 #1 to tug2 #7. rdi1i-rdi7i: the rdi1i to rdi7i bits identify the source of remote defect indication interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) mode, the associated rdi x i bit is unused and will return a logic 0 when read. when operational, the rdi1i to rdi7i bits report and acknowledge rdi interrupt of tu #2 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the received rdi state changes. an rdi x i bit is set high when a change of rdi state on the associated tributary (tu #2 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. rdi x i remains valid when interrupts are not enabled (rdie set low) and may be polled to detect change of remote defect indication events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 257 register 17ch, 27ch, 37ch: rtop, tu #2 in tug2 #1 to tug2 #7, rfi interrupt bit type function default bit 7 unused x bit 6 r rfi7i 0 bit 5 r rfi6i 0 bit 4 r rfi5i 0 bit 3 r rfi4i 0 bit 2 r rfi3i 0 bit 1 r rfi2i 0 bit 0 r rfi1i 0 this register is used to identify and acknowledge remote failure indication interrupts for the tributaries tu #2 in tug2 #1 to tug2 #7. rfi1i-rfi7i: the rfi1i to rfi7i bits identify the source of remote failure indication interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) mode, the associated rfi x i bit is unused and will return a logic 0 when read. when operational, the rfi1i to rfi7i bits report and acknowledge rfi interrupt of tu #2 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the received rfi state changes. an rfi x i bit is set high when a change of rfi state on the associated tributary (tu #2 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. rfi x i remains valid when interrupts are not enabled (rfie set low) and may be polled to detect change of remote failure indication events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 258 register 17dh, 27dh, 37dh: rtop, tu #2 in tug2 #1 to tug2 #7, in band error reporting configuration bit type function default bit 7 unused x bit 6 r/w iber7 0 bit 5 r/w iber6 0 bit 4 r/w iber5 0 bit 3 r/w iber4 0 bit 2 r/w iber3 0 bit 1 r/w iber2 0 bit 0 r/w iber1 0 this register enables the inband error reporting mode for the tributaries tu #2 in tug2 #1 to tug2 #7. iber1-iber7: the iber1 to iber7 bits control in band error reporting for tributary tu #2 in tug2 #1 to tug2 #7, respectively. setting an iber x bit high causes in band error reporting information to be inserted in the v5 byte of tributary tu #2 of the corresponding tug2. when an iber x bit is low, in band error reporting is disabled and the v5 byte of tributary tu #2 of the corresponding tug2 is not modified.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 259 register 17eh, 27eh, 37eh: tu #2 in tug2 #1 to tug2 #7, controllable output configuration bit type function default bit 7 unused x bit 6 r/w cout7 0 bit 5 r/w cout6 0 bit 4 r/w cout5 0 bit 3 r/w cout4 0 bit 2 r/w cout3 0 bit 1 r/w cout2 0 bit 0 r/w cout1 0 this register controls the cout output for the tributaries tu #2 in tug2 #1 to tug2 #7. cout1-cout7: the cout1 to cout7 bits control the cout output for tributary tu #2 in tug2 #1 to tug2 #7, respectively. setting a cout x bit high will force the cout output to be high when the incoming data stream is part of tributary tu #2 of the corresponding tug2. when an cout x bit is low, the cout output will be low when the incoming data stream is part of tributary tu #2 of the corresponding tug2.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 260 register 180h, 188h, 190h, 198h, 1a0h, 1a8h, 1b0h: register 280h, 288h, 290h, 298h, 2a0h, 2a8h, 2b0h: register 380h, 388h, 390h, 398h, 3a0h, 3a8h, 3b0h: rtop, tu #3 in tug2 #1 to tug2 #7, configuration bit type function default bit 7 r config[1] 1 bit 6 r config[0] 1 bit 5 r/w blkbip 0 bit 4 r/w pslue 0 bit 3 r/w pslme 0 bit 2 r/w copsle 0 bit 1 r/w rfie 0 bit 0 r/w rdie 0 this set of registers configures the operational modes of tu #3 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) or vt3 mode, the associated register in this set has no effect. rdie: the rdie bit enables the remote defect indication interrupt for tributary tu #1 in the corresponding tug2. when rdie is set high, an interrupt is generated upon changes of rdi status. interrupts due to rdi status change are masked when rdie is set low. the rdi status is derived from bit 8 of the v5 byte when rdiz7en is set low and from bits 5 to 7 of the z7 byte when rdiz7en is set high. rfie: the rfie bit enables the remote failure indication interrupt for tributary tu #1 in the corresponding tug2. when rdiz7en is set low, an interrupt is generated upon assertion and negation events of the rfiv bit when rfie is set high. interrupts due to rfiv status change are masked when rfie is set
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 261 low. when rdiz7en is set high, rfie is ignored. the rfie bit is not used when the rtop is in tu3 mode is enabled. copsle: the copsle bit enables the change of tributary path signal label interrupt for tributary tu #3 in the corresponding tug2. when copsle is set high, an interrupt is generated when the accepted path signal label changes. interrupts due to change of psl are masked when copsle is set low. pslme: the pslme bit enables the tributary path signal label mismatch interrupt for tributary tu #3 in the corresponding tug2. when pslme is set high, an interrupt is generated when the accepted path signal label changes from mismatching the provisioned psl to matching the provisioned value, or vice versa. interrupts due to psl mismatch status change are masked when pslme is set low. pslue: the pslue bit enables the tributary path signal label unstable interrupt for tributary tu #3 in the corresponding tug2. when pslue is set high, an interrupt is generated when the received path signal label becomes unstable or returns to stable. interrupts due to psl unstable status change are masked when pslue is set low. blkbip: the blkbip bit controls the accumulation of tributary bip-2 errors for the tributary tu #3 in the corresponding tug2. when blkbip is set high, bip-2 errors are counted on a block basis; the bip error count is incremented by one when one or both of the bip-2 bits are in error. when blkbip is set low, the bip error count is incremented once for each bip-2 bit that is in error. config[1:0]: the config[1:0] bits specify the tributary configuration of the corresponding tug2. the configuration specified by the config[1:0] bits are selected as follows:
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 262 config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 263 register 181h, 189h, 191h, 199h, 1a1h, 1a9h, 1b1h: register 281h, 289h, 291h, 299h, 2a1h, 2a9h, 2b1h: register 381h, 389h, 391h, 399h, 3a1h, 3a9h, 3b1h: rtop, tu #3 in tug2 #1 to tug2 #7, configuration and alarm status bit type function default bit 7 r/w rdiz7en 0 bit 6 r/w tupte 0 bit 5 r/w pdiven 0 bit 4 r psluv x bit 3 r pslmv x bit 2 r erdiv[2] x bit 1 r erdiv[1]/rfiv x bit 0 r erdiv[0]/rdiv x this set of registers reports alarm status and configures tu #3 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) or vt3 mode, the associated register in this set has no effect. rdiv: the rdiv bit indicates the remote defect indication status of tributary tu #3 in the corresponding tug2 when rdiz7en is low. rdiv is set high when the rdi bit in the v5 byte is set high for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers (addresses 0ch, 0dh, and 0eh). rdiv is set low when the rdi bit is set low for five or ten consecutive multiframes as determined by the rdi10 bit rfiv: the rfiv bit indicates the remote failure indication status of tributary tu #3 in the corresponding tug2 when rdiz7en is set low. rfiv is set high when the rfi bit in the v5 byte is set high for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 264 (addresses 0ch, 0dh, and 0eh). rfiv is set low when the rfi bit is set low for five or ten consecutive multiframes as determined by the rdi10 bit. erdiv[2:0]: the erdiv[2:0] bits indicates the extended remote defect indication status of tributary tu #3 in the corresponding tug2 when rdiz7en is set high. the erdiv[2:0] bits are set to a new code when the same code in the extended rdi bits of the z7 byte is seen for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers (addresses 0ch, 0dh, and 0eh). pslmv: the pslmv bit indicates the path signal mismatch status of tributary tu #3 in the corresponding tug2. pslmv is set high when the accepted psl differs from the provisioned value. pslmv is set low when the accepted psl has the same value as the provisioned one. psluv: the psluv bit indicates the path signal unstable status of tributary tu #3 in the corresponding tug2. the psl unstable counter is incremented if the psl of the current multiframe differs form that in the previous multiframe. the counter is cleared to zero when the same psl is received for five consecutive multiframes. the tributary psl unstable alarm is asserted and psluv set high when the unstable counter reaches five. the psl unstable alarm is negated and psluv set low when the unstable counter is cleared. pdiven: the pdiven bit modifies the payload defect indication status pdiv of tributary tu #3 in the corresponding tug2 . the pdiv output is set high when the psl in the v5 byte is set to the bit pattern specified by the pdicode[2:0] input for five consecutive multiframes. the pdiv output is set low when the psl is set to any other bit pattern for five consecutive multiframes. when pdiven is set high, the pdiv output is permanently set high independent of the tributary's defect status until the pdiven is set low. tupte: the tupte bit determines the alarm conditions under which ais is inserted for tributary tu #3 in the corresponding tug2. tupte is set high if tributary
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 265 tu #3 is to be terminated in the network element containing this tupp+622 device. in this case, tributary ais is automatically inserted based on the contents of the global tributary alarm ais control register (address 10h). tupte is set low if tributary tu #3 is part of the through traffic in the network element containing this tupp+622 device. in this case, tributary ais is only inserted when a loss of pointer (lop) or a loss of multiframe (lom) alarm is detected (as determined by the global tributary alarm ais control register). rdiz7en: the rdiz7en indicates which tributary path overhead byte is used for controlling the erdi[2:0] or rdi/rfi bits of tributary tu #3 in the corresponding tug2 . when rdiz7en is set low, the rdi and rfi bits in the v5 byte are used to control the rdiv and rfiv register bits. when rdiz7en is set high, the three bit extended rdi code in the z7 byte is used to control the erdiv[2:0] register bits.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 266 register 182h, 18ah, 192h, 19ah, 1a2h, 1aah, 1b2h: register 282h, 28ah, 292h, 29ah, 2a2h, 2aah, 2b2h: register 382h, 38ah, 392h, 39ah, 3a2h, 3aah, 3b2h: rtop, tu #3 in tug2 #1 to tug2 #7, expected path signal label bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w epsl[2] 0 bit 1 r/w epsl[1] 0 bit 0 r/w epsl[0] 0 this set of registers configures the expected the path signal label of tu #3 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) or vt3 mode, the associated register in this set has no effect. epsl[2:0]: the epsl[2:0] bits specifies the expected path signal label of tributary tu #3 in the corresponding tug2. the expected psl is compared with the accepted psl to determine the pslm state.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 267 register 183h, 18bh, 193h, 19bh, 1a3h, 1abh, 1b3h: register 283h, 28bh, 293h, 29bh, 2a3h, 2abh, 2b3h: register 383h, 38bh, 393h, 39bh, 3a3h, 3abh, 3b3h: rtop, tu #3 in tug2 #1 to tug2 #7, accepted path signal label bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r apsl[2] 0 bit 1 r apsl[1] 0 bit 0 r apsl[0] 0 this set of registers reports the accepted the path signal label of tu #3 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) or vt3 mode, the associated register in this set has no effect. apsl[2:0]: the apsl[2:0] bits report the accepted path signal label of tributary tu #3 in the corresponding tug2. an incoming psl is accepted when the same value is received for five consecutive multiframes.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 268 register 184h, 18ch, 194h, 19ch, 1a4h, 1ach, 1b4h: register 284h, 28ch, 294h, 29ch, 2a4h, 2ach, 2b4h: register 384h, 38ch, 394h, 39ch, 3a4h, 3ach, 3b4h: rtop, tu #3 in tug2 #1 to tug2 #7, bip-2 error count lsb bit type function default bit 7 r bip[7] x bit 6 r bip[6] x bit 5 r bip[5] x bit 4 r bip[4] x bit 3 r bip[3] x bit 2 r bip[2] x bit 1 r bip[1] x bit 0 r bip[0] x register 185h, 18dh, 195h, 19dh, 1a5h, 1adh, 1b5h: register 285h, 28dh, 295h, 29dh, 2a5h, 2adh, 2b5h: register 385h, 38dh, 395h, 39dh, 3a5h, 3adh, 3b5h: rtop, tu #3 in tug2 #1 to tug2 #7, bip-2 error count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r bip[10] x bit 1 r bip[9] x bit 0 r bip[8] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 269 these registers report the number of block interleave parity (bip-2) errors detected in tu #3 in tug2 #1 to tug2 #7 in the previous accumulation interval. these registers contain invalid data in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) or vt3 mode, the data in the associated registers are invalid. these registers do not saturate. bip[10:0]: the bip[10:0] bits report the number of tributary path bit-interleaved parity errors that have been detected since the last time the bip-2 registers were polled. the bip-2 registers are polled by writing to the input signal activity monitor, accumulate trigger register. the write access transfers the internally accumulated error count to the bip-2 registers within 10 s and resets the internal counter simultaneously to begin a new cycle of error accumulation.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 270 register 186h, 18eh, 196h, 19eh, 1a6h, 1aeh, 1b6h: register 286h, 28eh, 296h, 29eh, 2a6h, 2aeh, 2b6h: register 386h, 38eh, 396h, 39eh, 3a6h, 3aeh, 3b6h: tu #3 in tug2 #1 to tug2 #7, rei error count lsb bit type function default bit 7 r rei[7] x bit 6 r rei[6] x bit 5 r rei[5] x bit 4 r rei[4] x bit 3 r rei[3] x bit 2 r rei[2] x bit 1 r rei[1] x bit 0 r rei[0] x register 187h, 18fh, 197h, 19fh, 1a7h, 1afh, 1b7h: register 287h, 28fh, 297h, 29fh, 2a7h, 2afh, 2b7h: register 387h, 38fh, 397h, 39fh, 3a7h, 3afh, 3b7h: rtop, tu #3 in tug2 #1 to tug2 #7, rei error count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r rei[10] x bit 1 r rei[9] x bit 0 r rei[8] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 271 these registers report the number of remote error indications (rei) detected in tu #3 in tug2 #1 to tug2 #7 in the previous accumulation interval. these registers contain invaild data in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) or vt3 mode, the associated registers in this set contain invalid data. rei[10:0]: the rei[10:0] bits report the number of tributary path remote error indications that have been detected since the last time the rei registers were polled. the rei registers are polled by writing to the input signal activity monitor, accumulate trigger register. the write access transfers the internally accumulated error count to the rei registers within 10 s and resets the internal counter simultaneously to begin a new cycle of error accumulation.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 272 register 1b8h, 2b8h, 3b8h: rtop, tu #3 in tug2 #1 to tug2 #7, copsl interrupt bit type function default bit 7 reserved x bit 6 r copsl7i 0 bit 5 r copsl6i 0 bit 4 r copsl5i 0 bit 3 r copsl4i 0 bit 2 r copsl3i 0 bit 1 r copsl2i 0 bit 0 r copsl1i 0 this register is used to identify and acknowledge change of path signal label interrupts for the tributaries tu #3 in tug2 #1 to tug2 #7. copsl1i-copsl7i: the copsl1i to copsl7i bits identify the source of change of path signal label interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) or vt3 mode, the associated copsl x i bit is unused and will return a logic 0 when read. when operational, the copsl1i to copsl7i bits report and acknowledge copsl interrupt of tu #3 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the accepted psl changes. an copsl x i bit is set high when a change of psl event on the associated tributary (tu #3 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. copsl x i remains valid when interrupts are not enabled (copsle set low) and may be polled to detect change of path signal label events. reserved: the reserved bits must be written with a logic 0 for proper operation of the tupp+622.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 273 register 1b9h, 2b9h, 3b9h: rtop, tu #3 in tug2 #1 to tug2 #7, pslm interrupt bit type function default bit 7 unused x bit 6 r pslm7i 0 bit 5 r pslm6i 0 bit 4 r pslm5i 0 bit 3 r pslm4i 0 bit 2 r pslm3i 0 bit 1 r pslm2i 0 bit 0 r pslm1i 0 this register is used to identify and acknowledge path signal label mismatch interrupts for the tributaries tu #3 in tug2 #1 to tug2 #7. pslm1i-pslm7i: the pslm1i to pslm7i bits identify the source of path signal label mismatch interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) or vt3 mode, the associated pslm x i bit is unused and will return a logic 0 when read. when operational, the pslm1i to pslm7i bits report and acknowledge pslm interrupt of tu #3 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the accepted psl becomes matched to the expected psl or becomes mismatched to the expected psl. an pslm x i bit is set high when a change of psl matched state on the associated tributary (tu #3 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pslm x i remains valid when interrupts are not enabled (pslme set low) and may be polled to detect path signal label match/mismatch events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 274 register 1bah, 2bah, 3bah: rtop, tu #3 in tug2 #1 to tug2 #7, pslu interrupt bit type function default bit 7 unused x bit 6 r pslu7i 0 bit 5 r pslu6i 0 bit 4 r pslu5i 0 bit 3 r pslu4i 0 bit 2 r pslu3i 0 bit 1 r pslu2i 0 bit 0 r pslu1i 0 this register is used to identify and acknowledge path signal label unstable interrupts for the tributaries tu #3 in tug2 #1 to tug2 #7. pslu1i-pslu7i: the pslu1i to pslu7i bits identify the source of path signal label mismatch interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) or vt3 mode, the associated pslu x i bit is unused and will return a logic 0 when read. when operational, the pslu1i to pslu7i bits report and acknowledge pslu interrupt of tu #3 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the received psl becomes unstable or returns to stable. an pslu x i bit is set high when a change of psl unstable state on the associated tributary (tu #3 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pslu x i remains valid when interrupts are not enabled (pslue set low) and may be polled to detect path signal label stable/unstable events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 275 register 1bbh, 2bbh, 3bbh: rtop, tu #3 in tug2 #1 to tug2 #7, rdi interrupt bit type function default bit 7 unused x bit 6 r rdi7i 0 bit 5 r rdi6i 0 bit 4 r rdi5i 0 bit 3 r rdi4i 0 bit 2 r rdi3i 0 bit 1 r rdi2i 0 bit 0 r rdi1i 0 this register is used to identify and acknowledge remote defect indication interrupts for the tributaries tu #3 in tug2 #1 to tug2 #7. rdi1i-rdi7i: the rdi1i to rdi7i bits identify the source of remote defect indication interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) or vt3 mode, the associated rdi x i bit is unused and will return a logic 0 when read. when operational, the rdi1i to rdi7i bits report and acknowledge rdi interrupt of tu #3 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the received rdi state changes. an rdi x i bit is set high when a change of rdi state on the associated tributary (tu #3 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. rdi x i remains valid when interrupts are not enabled (rdie set low) and may be polled to detect change of remote defect indication events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 276 register 1bch, 2bch, 3bch: rtop, tu #3 in tug2 #1 to tug2 #7, rfi interrupt bit type function default bit 7 unused x bit 6 r rfi7i 0 bit 5 r rfi6i 0 bit 4 r rfi5i 0 bit 3 r rfi4i 0 bit 2 r rfi3i 0 bit 1 r rfi2i 0 bit 0 r rfi1i 0 this register is used to identify and acknowledge remote failure indication interrupts for the tributaries tu #3 in tug2 #1 to tug2 #7. rfi1i-rfi7i: the rfi1i to rfi7i bits identify the source of remote failure indication interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) or vt3 mode, the associated rfi x i bit is unused and will return a logic 0 when read. when operational, the rfi1i to rfi7i bits report and acknowledge rfi interrupt of tu #3 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the received rfi state changes. an rfi x i bit is set high when a change of rfi state on the associated tributary (tu #3 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. rfi x i remains valid when interrupts are not enabled (rfie set low) and may be polled to detect change of remote failure indication events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 277 register 1bdh, 2bdh, 3bdh: rtop, tu #3 in tug2 #1 to tug2 #7, in band error reporting configuration bit type function default bit 7 unused x bit 6 r/w iber7 0 bit 5 r/w iber6 0 bit 4 r/w iber5 0 bit 3 r/w iber4 0 bit 2 r/w iber3 0 bit 1 r/w iber2 0 bit 0 r/w iber1 0 this register enables the inband error reporting mode for the tributaries tu #3 in tug2 #1 to tug2 #7. iber1-iber7: the iber1 to iber7 bits control in band error reporting for tributary tu #3 in tug2 #1 to tug2 #7, respectively. setting an iber x bit high causes in band error reporting information to be inserted in the v5 byte of tributary tu #3 of the corresponding tug2. when an iber x bit is low, in band error reporting is disabled and the v5 byte of tributary tu #3 of the corresponding tug2 is not modified.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 278 register 1beh, 2beh, 3beh: rtop, tu #3 in tug2 #1 to tug2 #7, controllable output configuration bit type function default bit 7 unused x bit 6 r/w cout7 0 bit 5 r/w cout6 0 bit 4 r/w cout5 0 bit 3 r/w cout4 0 bit 2 r/w cout3 0 bit 1 r/w cout2 0 bit 0 r/w cout1 0 this register controls the cout output for the tributaries tu #3 in tug2 #1 to tug2 #7. cout1-cout7: the cout1 to cout7 bits control the cout output for tributary tu #3 in tug2 #1 to tug2 #7, respectively. setting a cout x bit high will force the cout output to be high when the incoming data stream is part of tributary tu #3 of the corresponding tug2. when an cout x bit is low, the cout output will be low when the incoming data stream is part of tributary tu #3 of the corresponding tug2.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 279 register 1c0h, 1c8h, 1d0h, 1d8h, 1e0h, 1e8h, 1f0h: register 2c0h, 2c8h, 2d0h, 2d8h, 2e0h, 2e8h, 2f0h: register 3c0h, 3c8h, 3d0h, 3d8h, 3e0h, 3e8h, 3f0h: rtop, tu #4 in tug2 #1 to tug2 #7, configuration bit type function default bit 7 r config[1] 1 bit 6 r config[0] 1 bit 5 r/w blkbip 0 bit 4 r/w pslue 0 bit 3 r/w pslme 0 bit 2 r/w copsle 0 bit 1 r/w rfie 0 bit 0 r/w rdie 0 this set of registers configures the operational modes of tu #4 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6), vt3 or tu12 (vt2) mode, the associated register in this set has no effect. rdie: the rdie bit enables the remote defect indication interrupt for tributary tu #4 in the corresponding tug2. when rdiz7en is set low, an interrupt is generated upon assertion and negation events of the rdiv bit when rdie is set high. interrupts due to rdiv status change are masked when rdie is set low. when rdiz7en is set high, an interrupt is generated upon assertion or negation events of the erdiv[2:0] bits when rdie is set high. interrupts due to erdiv[2:0] status change are masked when rdie is set low. copsle: the copsle bit enables the change of tributary path signal label interrupt for tributary tu #4 in the corresponding tug2. when copsle is set high, an
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 280 interrupt is generated when the accepted path signal label changes. interrupts due to change of psl are masked when copsle is set low. pslme: the pslme bit enables the tributary path signal label mismatch interrupt for tributary tu #4 in the corresponding tug2. when pslme is set high, an interrupt is generated when the accepted path signal label changes from mismatching the provisioned psl to matching the provisioned value, or vice versa. interrupts due to psl mismatch status change are masked when pslme is set low. pslue: the pslue bit enables the tributary path signal label unstable interrupt for tributary tu #4 in the corresponding tug2. when pslue is set high, an interrupt is generated when the received path signal label becomes unstable or returns to stable. interrupts due to psl unstable status change are masked when pslue is set low. blkbip: the blkbip bit controls the accumulation of tributary bip-2 errors for the tributary tu #4 in the corresponding tug2. when blkbip is set high, bip-2 errors are counted on a block basis; the bip error count is incremented by one when one or both of the bip-2 bits are in error. when blkbip is set low, the bip error count is incremented once for each bip-2 bit that is in error. config[1:0]: the config[1:0] bits specify the tributary configuration of the corresponding tug2. the configuration specified by the config[1:0] bits are selected as follows: config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 281 register 1c1h, 1c9h, 1d1h, 1d9h, 1e1h, 1e9h, 1f1h: register 2c1h, 2c9h, 2d1h, 2d9h, 2e1h, 2e9h, 2f1h: register 3c1h, 3c9h, 3d1h, 3d9h, 3e1h, 3e9h, 3f1h: rtop, tu #4 in tug2 #1 to tug2 #7, configuration and alarm status bit type function default bit 7 r/w rdiz7en 0 bit 6 r/w tupte 0 bit 5 r/w pdiven 0 bit 4 r psluv x bit 3 r pslmv x bit 2 r erdiv[2] x bit 1 r erdiv[1]/rfiv x bit 0 r erdiv[0]/rdiv x this set of registers configures and reports the alarm status of tu #4 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6), vt3 or tu12 (vt2) mode, the associated register in this set has no effect. rdiv: the rdiv bit indicates the remote defect indication status of tributary tu #4 in the corresponding tug2 when rdiz7en is low. rdiv is set high when the rdi bit in the v5 byte is set high for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers (addresses 0ch, 0dh, and 0eh). rdiv is set low when the rdi bit is set low for five or ten consecutive multiframes as determined by the rdi10 bit rfiv: the rfiv bit indicates the remote failure indication status of tributary tu #4 in the corresponding tug2 when rdiz7en is set low. rfiv is set high when the rfi bit in the v5 byte is set high for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 282 (addresses 0ch, 0dh, and 0eh). rfiv is set low when the rfi bit is set low for five or ten consecutive multiframes as determined by the rdi10 bit. erdiv[2:0]: the erdiv[2:0] bits indicates the extended remote defect indication status of tributary tu #4 in the corresponding tug2 when rdiz7en is set high. the erdiv[2:0] bits are set to a new code when the same code in the extended rdi bits of the z7 byte is seen for five or ten consecutive multiframes as determined by the rdi10 bit in the rtop and rttb configuration registers (addresses 0ch, 0dh, and 0eh). pslmv: the pslmv bit indicates the path signal mismatch status of tributary tu #4 in the corresponding tug2. pslmv is set high when the accepted psl differs from the provisioned value. pslmv is set low when the accepted psl has the same value as the provisioned one. psluv: the psluv bit indicates the path signal unstable status of tributary tu #4 in the corresponding tug2. the psl unstable counter is incremented if the psl of the current multiframe differs form that in the previous multiframe. the counter is cleared to zero when the same psl is received for five consecutive multiframes. the tributary psl unstable alarm is asserted and psluv set high when the unstable counter reaches five. the psl unstable alarm is negated and psluv set low when the unstable counter is cleared. pdiven: the pdiven bit modifies the payload defect indication status pdiv of tributary tu #4 in the corresponding tug2 . the pdiv output is set high when the psl in the v5 byte is set to the bit pattern specified by the pdicode[2:0] input for five consecutive multiframes. the pdiv output is set low when the psl is set to any other bit pattern for five consecutive multiframes. when pdiven is set high, the pdiv output is permanently set high independent of the tributary's defect status until the pdiven is set low. tupte: the tupte bit determines the alarm conditions under which ais is inserted for tributary tu #4 in the corresponding tug2. tupte is set high if tributary
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 283 tu #4 is to be terminated in the network element containing this tupp+622 device. in this case, tributary ais is automatically inserted based on the contents of the global tributary alarm ais control register (address 10h). tupte is set low if tributary tu #4 is part of the through traffic in the network element containing this tupp+622 device. in this case, tributary ais is only inserted when a loss of pointer (lop) or a loss of multiframe (lom) alarm is detected (as determined by the global tributary alarm ais control register). rdiz7en: the rdiz7en indicates which tributary path overhead byte is used for controlling the erdi[2:0] or rdi/rfi bits of tributary tu #4 in the corresponding tug2 . when rdiz7en is set low, the rdi and rfi bits in the v5 byte are used to control the rdiv and rfiv register bits. when rdiz7en is set high, the three bit extended rdi code in the z7 byte is used to control the erdiv[2:0] register bits.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 284 register 1c2h, 1cah, 1d2h, 1dah, 1e2h, 1eah, 1f2h: register 2c2h, 2cah, 2d2h, 2dah, 2e2h, 2eah, 2f2h: register 3c2h, 3cah, 3d2h, 3dah, 3e2h, 3eah, 3f2h: rtop, tu #4 in tug2 #1 to tug2 #7, expected path signal label bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w epsl[2] 0 bit 1 r/w epsl[1] 0 bit 0 r/w epsl[0] 0 this set of registers configures the expected path signal label of tu #4 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6), vt3 or tu12 (vt2) mode, the associated register in this set has no effect. epsl[2:0]: the epsl[2:0] bits specifies the expected path signal label of tributary tu #4 in the corresponding tug2. the expected psl is compared with the accepted psl to determine the pslm state.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 285 register 1c3h, 1cbh, 1d3h, 1dbh, 1e3h, 1ebh, 1f3h: register 2c3h, 2cbh, 2d3h, 2dbh, 2e3h, 2ebh, 2f3h: register 3c3h, 3cbh, 3d3h, 3dbh, 3e3h, 3ebh, 3f3h: rtop, tu #4 in tug2 #1 to tug2 #7, path signal label bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r apsl[2] 0 bit 1 r apsl[1] 0 bit 0 r apsl[0] 0 this set of register reports the accepted path signal label of tu #4 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6), vt3 or tu12 (vt2) mode, the associated register in this set has no effect. apsl[2:0]: the apsl[2:0] bits report the accepted path signal label of tributary tu #4 in the corresponding tug2. an incoming psl is accepted when the same value is received for five consecutive multiframes.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 286 register 1c4h, 1cch, 1d4h, 1dch, 1e4h, 1ech, 1f4h: register 2c4h, 2cch, 2d4h, 2dch, 2e4h, 2ech, 2f4h: register 3c4h, 3cch, 3d4h, 3dch, 3e4h, 3ech, 3f4h: rtop, tu #4 in tug2 #1 to tug2 #7, bip-2 error count lsb bit type function default bit 7 r bip[7] x bit 6 r bip[6] x bit 5 r bip[5] x bit 4 r bip[4] x bit 3 r bip[3] x bit 2 r bip[2] x bit 1 r bip[1] x bit 0 r bip[0] x register 1c5h, 1cdh, 1d5h, 1ddh, 1e5h, 1edh, 1f5h: register 2c5h, 2cdh, 2d5h, 2ddh, 2e5h, 2edh, 2f5h: register 3c5h, 3cdh, 3d5h, 3ddh, 3e5h, 3edh, 3f5h: rtop, tu #4 in tug2 #1 to tug2 #7, bip-2 error count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r bip[10] x bit 1 r bip[9] x bit 0 r bip[8] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 287 these registers report the number of block interleave parity (bip-2) errors detected in tu #4 in tug2 #1 to tug2 #7 in the previous accumulation interval. these registers contain invalid data in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6), vt3 or tu12 (vt2) mode, the associated registers in this set contain invalid data. these registers do not saturate. bip[10:0]: the bip[10:0] bits report the number of tributary path bit-interleaved parity errors that have been detected since the last time the bip-2 registers were polled. the bip-2 registers are polled by writing to the input signal activity monitor, accumulate trigger register. the write access transfers the internally accumulated error count to the bip-2 registers within 10 s and resets the internal counter simultaneously to begin a new cycle of error accumulation.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 288 register 1c6h, 1ceh, 1d6h, 1deh, 1e6h, 1eeh, 1f6h: register 2c6h, 2ceh, 2d6h, 2deh, 2e6h, 2eeh, 2f6h: register 3c6h, 3ceh, 3d6h, 3deh, 3e6h, 3eeh, 3f6h: rtop, tu #4 in tug2 #1 to tug2 #7, rei error count lsb bit type function default bit 7 r rei[7] x bit 6 r rei[6] x bit 5 r rei[5] x bit 4 r rei[4] x bit 3 r rei[3] x bit 2 r rei[2] x bit 1 r rei[1] x bit 0 r rei[0] x register 1c7h, 1cfh, 1d7h, 1dfh, 1e7h, 1efh, 1f7h: register 2c7h, 2cfh, 2d7h, 2dfh, 2e7h, 2efh, 2f7h: register 3c7h, 3cfh, 3d7h, 3dfh, 3e7h, 3efh, 3f7h: rtop, tu #4 in tug2 #1 to tug2 #7, rei error count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r rei[10] x bit 1 r rei[9] x bit 0 r rei[8] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 289 these registers report the number of remote error indications (rei) detected in tu #4 in tug2 #1 to tug2 #7 in the previous accumulation interval. these registers contain invalid data in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6), vt3 or tu12 (vt2) mode, the associated registers in this set contain invalid data. rei[10:0]: the rei[10:0] bits report the number of tributary path remote error indications that have been detected since the last time the rei registers were polled. the rei registers are polled by writing to the input signal activity monitor, accumulate trigger register. the write access transfers the internally accumulated error count to the rei registers within 10 s and resets the internal counter simultaneoulsly to begin a new cycle of error accumulation.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 290 register 1f8h, 2f8h, 3f8h: rtop, tu #4 in tug2 #1 to tug2 #7, copsl interrupt bit type function default bit 7 unused 0 bit 6 r copsl7i 0 bit 5 r copsl6i 0 bit 4 r copsl5i 0 bit 3 r copsl4i 0 bit 2 r copsl3i 0 bit 1 r copsl2i 0 bit 0 r copsl1i 0 this register is used to identify and acknowledge change of path signal label interrupts for the tributaries tu #4 in tug2 #1 to tug2 #7. copsl1i-copsl7i: the copsl1i to copsl7i bits identify the source of change of path signal label interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6), vt3 or tu12 (vt2) mode, the associated copsl x i bit is unused and will return a logic 0 when read. when operational, the copsl1i to copsl7i bits report and acknowledge copsl interrupt of tu #4 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the accepted psl changes. an copsl x i bit is set high when a change of psl event on the associated tributary (tu #4 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. copsl x i remains valid when interrupts are not enabled (copsle set low) and may be polled to detect change of path signal label events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 291 register 1f9h, 2f9h, 3f9h: rtop, tu #4 in tug2 #1 to tug2 #7, pslm interrupt bit type function default bit 7 unused x bit 6 r pslm7i 0 bit 5 r pslm6i 0 bit 4 r pslm5i 0 bit 3 r pslm4i 0 bit 2 r pslm3i 0 bit 1 r pslm2i 0 bit 0 r pslm1i 0 this register is used to identify and acknowledge path signal label mismatch interrupts for the tributaries tu #4 in tug2 #1 to tug2 #7. pslm1i-pslm7i: the pslm1i to pslm7i bits identify the source of path signal label mismatch interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6), vt3 or tu12 (vt2) mode, the associated pslm x i bit is unused and will return a logic 0 when read. when operational, the pslm1i to pslm7i bits report and acknowledge pslm interrupt of tu #4 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the accepted psl becomes matched to the expected psl or becomes mismatched to the expected psl. an pslm x i bit is set high when a change of psl matched state on the associated tributary (tu #4 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pslm x i remains valid when interrupts are not enabled (pslme set low) and may be polled to detect path signal label match/mismatch events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 292 register 1fah, 2fah, 3fah: rtop, tu #4 in tug2 #1 to tug2 #7, pslu interrupt bit type function default bit 7 unused x bit 6 r pslu7i 0 bit 5 r pslu6i 0 bit 4 r pslu5i 0 bit 3 r pslu4i 0 bit 2 r pslu3i 0 bit 1 r pslu2i 0 bit 0 r pslu1i 0 this register is used to identify and acknowledge path signal label unstable interrupts for the tributaries tu #4 in tug2 #1 to tug2 #7. pslu1i-pslu7i: the pslu1i to pslu7i bits identify the source of path signal label mismatch interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6), vt3 or tu12 (vt2) mode, the associated pslu x i bit is unused and will return a logic 0 when read. when operational, the pslu1i to pslu7i bits report and acknowledge pslu interrupt of tu #4 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the received psl becomes unstable or returns to stable. an pslu x i bit is set high when a change of psl unstable state on the associated tributary (tu #4 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. pslu x i remains valid when interrupts are not enabled (pslue set low) and may be polled to detect path signal label stable/unstable events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 293 register 1fbh, 2fbh, 3fbh: rtop, tu #4 in tug2 #1 to tug2 #7, rdi interrupt bit type function default bit 7 unused x bit 6 r rdi7i 0 bit 5 r rdi6i 0 bit 4 r rdi5i 0 bit 3 r rdi4i 0 bit 2 r rdi3i 0 bit 1 r rdi2i 0 bit 0 r rdi1i 0 this register is used to identify and acknowledge remote defect indication interrupts for the tributaries tu #4 in tug2 #1 to tug2 #7. rdi1i-rdi7i: the rdi1i to rdi7i bits identify the source of remote defect indication interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6), vt3 or tu12 (vt2) mode, the associated rdi x i bit is unused and will return a logic 0 when read. when operational, the rdi1i to rdi7i bits report and acknowledge rdi interrupt of tu #4 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the received rdi state changes. an rdi x i bit is set high when a change of rdi state on the associated tributary (tu #4 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. rdi x i remains valid when interrupts are not enabled (rdie set low) and may be polled to detect change of remote defect indication events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 294 register 1fch, 2fch, 3fch: rtop, tu #4 in tug2 #1 to tug2 #7, rfi interrupt bit type function default bit 7 unused x bit 6 r rfi7i 0 bit 5 r rfi6i 0 bit 4 r rfi5i 0 bit 3 r rfi4i 0 bit 2 r rfi3i 0 bit 1 r rfi2i 0 bit 0 r rfi1i 0 this register is used to identify and acknowledge remote failure indication interrupts for the tributaries tu #4 in tug2 #1 to tug2 #7. rfi1i-rfi7i: the rfi1i to rfi7i bits identify the source of remote failure indication interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6), vt3 or tu12 (vt2) mode, the associated rfi x i bit is unused and will return a logic 0 when read. when operational, the rfi1i to rfi7i bits report and acknowledge rfi interrupt of tu #4 in tug2 #1 to tug2 #7, respectively. interrupts are generated when the received rfi state changes. an rfi x i bit is set high when a change of rfi state on the associated tributary (tu #4 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. rfi x i remains valid when interrupts are not enabled (rfie set low) and may be polled to detect change of remote failure indication events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 295 register 1fdh, 2fdh, 3fdh: rtop, tu #4 in tug2 #1 to tug2 #7, in band error reporting configuration bit type function default bit 7 unused x bit 6 r/w iber7 0 bit 5 r/w iber6 0 bit 4 r/w iber5 0 bit 3 r/w iber4 0 bit 2 r/w iber3 0 bit 1 r/w iber2 0 bit 0 r/w iber1 0 this register enables the inband error reporting mode for the tributaries tu #4 in tug2 #1 to tug2 #7. iber1-iber7: the iber1 to iber7 bits control in band error reporting for tributary tu #4 in tug2 #1 to tug2 #7, respectively. setting an iber x bit high causes in band error reporting information to be inserted in the v5 byte of tributary tu #4 of the corresponding tug2. when an iber x bit is low, in band error reporting is disabled and the v5 byte of tributary tu #4 of the corresponding tug2 is not modified.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 296 register 1feh, 2feh, 3feh: rtop, tu #4 in tug2 #1 to tug2 #7, controllable output configuration bit type function default bit 7 unused x bit 6 r/w cout7 0 bit 5 r/w cout6 0 bit 4 r/w cout5 0 bit 3 r/w cout4 0 bit 2 r/w cout3 0 bit 1 r/w cout2 0 bit 0 r/w cout1 0 this register controls the cout output for the tributaries tu #4 in tug2 #1 to tug2 #7. cout1-cout7: the cout1 to cout7 bits control the cout output for tributary tu #4 in tug2 #1 to tug2 #7, respectively. setting a cout x bit high will force the cout output to be high when the incoming data stream is part of tributary tu #4 of the corresponding tug2. when an cout x bit is low, the cout output will be low when the incoming data stream is part of tributary tu #4 of the corresponding tug2.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 297 register 1ffh, 2ffh, 3ffh: rtop status bit type function default bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r/w blkrei 0 bit 0 r busy x this register configures and reports the status of the various internal operations inside rtop. busy: the busy bit indicates the status of the transfer of bip and rei counts from the counters to the holding registers. busy is set high when the stp input signal activity monitor #1, accumulation trigger register is being written. busy is set low when all the counters values have been transferred to holding registers. the elapsed time shall be less than 10 s. blkrei: the block rei accumulation control bit selects between counting of reis in the incoming tu3 stream on a block or bit basis. when blkrei is set high, rei count codes in the range of 1 to 8 are accumulated on a block basis as a single rei event. all other codes are counted zero events. when blkrei is set low, rei count codes in the range of 1 to 8 are accumulated on a bit basis as a up to 8 rei events. all other codes are counted zero events. reserved: the reserved bits must be written with a logic 0 for proper operation of the tupp+622.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 298 11.4 rttb #1, rttb #2 and rttb #3 registers register 400h, 440h, 480h: rttb, tu3 or tu #1 in tug2 #1, configuration and status bit type function default bit 7 r/w config[1] 1 bit 6 r/w config[0] 1 bit 5 r/w nosync 0 bit 4 r/w len16 0 bit 3 r timv x bit 2 r/w time 0 bit 1 r tiuv x bit 0 r/w tiue 0 in tu3 mode (tu3 bit in vtpp configuration register set high), this register reports the status and configures operational modes of the tu3 mapped into a tug3 handled by the rttb. out of tu3 mode, this register reports the status and configures the operational modes of tu #1 in tug2 #1. tiue: the tiue bit enables trail trace identifier unstable interrupts for tributary tu #1 in tug2 #1 or tu3 when tiue is set high, an interrupt is generated upon detection of an unstable identifier and upon return to a stable identifier. interrupts due to tiu status change are masked when tiue is set low. tiuv: the tiuv bit indicates the trail trace identifier unstable status of tributary tu #1 in tug2 #1 or tu3. time: the time bit enables trail trace identifier mismatch interrupts for tributary tu #1 in tug2 #1 or tu3. when time is set high, an interrupt is generated upon detection of a mismatched identifier and upon return to a matched
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 299 identifier. interrupts due to tim status change are masked when time is set low. timv: the tiuv bit indicates the trail trace identifier mismatch status of tributary tu #1 in tug2 #1 or tu3. len16: the path trace message length bit (len16) selects the length of the path trace message to be 16 bytes or 64 bytes for tributary tu #1 in tug2 #1 or tu3. when len16 is set high, the message length is set to 16 bytes. when len16 is set low, the message length is set to 64 bytes. nosync: the path trace message synchronization disable bit (nosync) disables the synchronized writing of the path trace message into the trace buffer based on the contents of the message for tributary tu #1 in tug2 #1 or tu3. when len16 is set high and nosync is set low, the receive path trace message byte with its most significant bit set to logic one will be written to the first location in the buffer. when len16 is set low, and nosync is also set low, the byte after the carriage return/linefeed (cr/lf) sequence will be written to the first location in the buffer. when nosync is set high, synchronization is disabled, and the path trace message buffer behaves as a circular buffer. config[1:0]: the config[1:0] bits specify the tributary configuration of tributary group tug2 #1. the config[1:0] bits have no effect in tu3 mode. the configuration specified by the config[1:0] bits are selected as follows: config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 300 register 401h-406h, 441h-446h, 481h-486h: rttb, tu #1 in tug2 #2 to tug2 #7, configuration and status bit type function default bit 7 r/w config[1] 1 bit 6 r/w config[0] 1 bit 5 r/w nosync 0 bit 4 r/w len16 0 bit 3 r timv x bit 2 r/w time 0 bit 1 r tiuv x bit 0 r/w tiue 0 this set of registers reports the status and configures the operational modes of tu #1 in tug2 #2 to tug2 #7. these registers have no effect in tu3 mode. tiue: the tiue bit enables trail trace identifier unstable interrupts for tributary tu #1 in the corresponding tug2. when tiue is set high, an interrupt is generated upon detection of an unstable identifier and upon return to a stable identifier. interrupts due to tiu status change are masked when tiue is set low. tiuv: the tiuv bit indicates the trail trace identifier unstable status of tributary tu #1 in the corresponding tug2. time: the time bit enables trail trace identifier mismatch interrupts for tributary tu #1 in the corresponding tug2. when time is set high, an interrupt is generated upon detection of a mismatched identifier and upon return to a matched identifier. interrupts due to tim status change are masked when time is set low.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 301 timv: the timv bit indicates the trail trace identifier mismatch status of tributary tu #1 in the corresponding tug2. len16: the path trace message length bit (len16) selects the length of the path trace message to be 16 bytes or 64 bytes for tributary tu #1 in the corresponding tug2. when len16 is set high, the message length is set to 16 bytes. when len16 is set low, the message length is set to 64 bytes. nosync: the path trace message synchronization disable bit (nosync) disables the synchronized writing of the path trace message into the trace buffer based on the contents of the message for tributary tu #1 in the corresponding tug2. when len16 is set high and nosync is set low, the receive path trace message byte with its most significant bit set to logic one will be written to the first location in the buffer. when len16 is set low, and nosync is also set low, the byte after the carriage return/linefeed (cr/lf) sequence will be written to the first location in the buffer. when nosync is set high, synchronization is disabled, and the path trace message buffer behaves as a circular buffer. config[1:0]: the config[1:0] bits specify the tributary configuration of the corresponding tributary group tug2. the configuration specified by the config[1:0] bits are selected as follows: config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 302 register 408h-40eh, 448h-44eh, 488h-48eh: rttb, tu #2 in tug2 #1 to tug2 #7, configuration and status bit type function default bit 7 r config[1] 1 bit 6 r config[0] 1 bit 5 r/w nosync 0 bit 4 r/w len16 0 bit 3 r timv x bit 2 r/w time 0 bit 1 r tiuv x bit 0 r/w tiue 0 this set of registers reports the status and configures the operational modes of tu #2 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) mode, the associated register in this set has no effect. tiue: the tiue bit enables trail trace identifier unstable interrupts for tributary tu #2 in the corresponding tug2. when tiue is set high, an interrupt is generated upon detection of an unstable identifier and upon return to a stable identifier. interrupts due to tiu status change are masked when tiue is set low. tiuv: the tiuv bit indicates the trail trace identifier unstable status of tributary tu #2 in the corresponding tug2. time: the time bit enables trail trace identifier mismatch interrupts for tributary tu #2 in the corresponding tug2. when time is set high, an interrupt is generated upon detection of a mismatched identifier and upon return to a
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 303 matched identifier. interrupts due to tim status change are masked when time is set low. timv: the timv bit indicates the trail trace identifier mismatch status of tributary tu #2 in the corresponding tug2. len16: the path trace message length bit (len16) selects the length of the path trace message to be 16 bytes or 64 bytes for tributary tu #2 in the corresponding tug2. when len16 is set high, the message length is set to 16 bytes. when len16 is set low, the message length is set to 64 bytes. nosync: the path trace message synchronization disable bit (nosync) disables the synchronized writing of the path trace message into the trace buffer based on the contents of the message for tributary tu #2 in the corresponding tug2. when len16 is set high and nosync is set low, the receive path trace message byte with its most significant bit set to logic one will be written to the first location in the buffer. when len16 is set low, and nosync is also set low, the byte after the carriage return/linefeed (cr/lf) sequence will be written to the first location in the buffer. when nosync is set high, synchronization is disabled, and the path trace message buffer behaves as a circular buffer. config[1:0]: the config[1:0] bits specify the tributary configuration of the corresponding tributary group tug2. the configuration specified by the config[1:0] bits are selected as follows: config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 304 register 410h-416h, 450h-456h, 490h-496h: rttb, tu #3 in tug2 #1 to tug2 #7, configuration and status bit type function default bit 7 r config[1] 1 bit 6 r config[0] 1 bit 5 r/w nosync 0 bit 4 r/w len16 0 bit 3 r timv x bit 2 r/w time 0 bit 1 r tiuv x bit 0 r/w tiue 0 this set of registers reports the status and configures the operational modes of tu #3 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6) or vt3 mode, the associated register in this set has no effect. tiue: the tiue bit enables trail trace identifier unstable interrupts for tributary tu #3 in the corresponding tug2. when tiue is set high, an interrupt is generated upon detection of an unstable identifier and upon return to a stable identifier. interrupts due to tiu status change are masked when tiue is set low. tiuv: the tiuv bit indicates the trail trace identifier unstable status of tributary tu #3 in the corresponding tug2. time: the time bit enables trail trace identifier mismatch interrupts for tributary tu #3 in the corresponding tug2. when time is set high, an interrupt is generated upon detection of a mismatched identifier and upon return to a
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 305 matched identifier. interrupts due to tim status change are masked when time is set low. timv: the timv bit indicates the trail trace identifier mismatch status of tributary tu #3 in the corresponding tug2. len16: the path trace message length bit (len16) selects the length of the path trace message to be 16 bytes or 64 bytes for tributary tu #3 in the corresponding tug2. when len16 is set high, the message length is set to 16 bytes. when len16 is set low, the message length is set to 64 bytes. nosync: the path trace message synchronization disable bit (nosync) disables the synchronized writing of the path trace message into the trace buffer based on the contents of the message for tributary tu #3 in the corresponding tug2. when len16 is set high and nosync is set low, the receive path trace message byte with its most significant bit set to logic one will be written to the first location in the buffer. when len16 is set low, and nosync is also set low, the byte after the carriage return/linefeed (cr/lf) sequence will be written to the first location in the buffer. when nosync is set high, synchronization is disabled, and the path trace message buffer behaves as a circular buffer. config[1:0]: the config[1:0] bits specify the tributary configuration of the corresponding tributary group tug2. the configuration specified by the config[1:0] bits are selected as follows: config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 306 register 418h-41eh, 458h-45eh, 498h-49eh: rttb, tu #4 in tug2 #1 to tug2 #7, configuration and status bit type function default bit 7 r config[1] 1 bit 6 r config[0] 1 bit 5 r/w nosync 0 bit 4 r/w len16 0 bit 3 r timv x bit 2 r/w time 0 bit 1 r tiuv x bit 0 r/w tiue 0 this set of registers reports the status and configures the operational modes of tu #4 in tug2 #1 to tug2 #7. these registers have no effect in tu3 mode. when the corresponding tug2 tributary group is configured to tu2 (vt6), vt3 or, tu12 (vt2) mode, the associated register in this set has no effect. tiue: the tiue bit enables trail trace identifier unstable interrupts for tributary tu #4 in the corresponding tug2. when tiue is set high, an interrupt is generated upon detection of an unstable identifier and upon return to a stable identifier. interrupts due to tiu status change are masked when tiue is set low. tiuv: the tiuv bit indicates the trail trace identifier unstable status of tributary tu #4 in the corresponding tug2. time: the time bit enables trail trace identifier mismatch interrupts for tributary tu #4 in the corresponding tug2. when time is set high, an interrupt is generated upon detection of a mismatched identifier and upon return to a
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 307 matched identifier. interrupts due to tim status change are masked when time is set low. timv: the tiuv bit indicates the trail trace identifier mismatch status of tributary tu #4 in the corresponding tug2. len16: the path trace message length bit (len16) selects the length of the path trace message to be 16 bytes or 64 bytes for tributary tu #4 in the corresponding tug2. when len16 is set high, the message length is set to 16 bytes. when len16 is set low, the message length is set to 64 bytes. nosync: the path trace message synchronization disable bit (nosync) disables the synchronized writing of the path trace message into the trace buffer based on the contents of the message for tributary tu #4 in the corresponding tug2. when len16 is set high and nosync is set low, the receive path trace message byte with its most significant bit set to logic one will be written to the first location in the buffer. when len16 is set low, and nosync is also set low, the byte after the carriage return/linefeed (cr/lf) sequence will be written to the first location in the buffer. when nosync is set high, synchronization is disabled, and the path trace message buffer behaves as a circular buffer. config[1:0]: the config[1:0] bits specify the tributary configuration of the corresponding tributary group tug2. the configuration specified by the config[1:0] bits are selected as follows: config[1] config[0] configuration active tu (vt) 00tu2 (vt6)#1 0 1 vt3 #1, #2 1 0 tu12 (vt2) #1, #2, #3 1 1 tu11 (vt1.5) #1, #2, #3, #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 308 register 420h, 460h, 4a0h: rttb, tu3 or tu #1 in tug2 #1 to tug2 #7, tim interrupt bit type function default bit 7 unused x bit 6 r tim7i 0 bit 5 r tim6i 0 bit 4 r tim5i 0 bit 3 r tim4i 0 bit 2 r tim3i 0 bit 1 r tim2i 0 bit 0 r tim1i 0 this register is used to identify and acknowledge trail trace identifier mismatch interrupts for the tributaries tu #1 in tug2 #1 to tug2 #7. it is also used to identify and acknowledge tu3 trail trace identifier mismatch interrupts. tim1i: the tim1i bit identifies the source of trail trace identifier mismatch interrupts. in tu3 mode, the tim1i bit reports and acknowledges tim interrupt of the tu3 trail trace identifier. out of tu3 mode, tim1i bit reports and acknowledges tim interrupt of tu #1 in tug2 #1. interrupts are generated upon change of identifier mismatch state. the tim1i bit is set high when a trail trace identifier mismatch event and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. the tim1i bit remains valid when interrupts are not enabled (time set low) and may be polled to detect trail trace identifier mismatch events. tim2i-tim7i: the tim2i to tim7i bits identify the source of trail trace identifier mismatch interrupts. tim2i to tim7i bits report and acknowledge tim interrupt of tu #1 in tug2 #2 to tug2 #7, respectively. interrupts are generated upon change of identifier mismatch state. an tim x i bit is set high when a trail trace identifier mismatch event on the corresponding tributary (tu #1 in tug2 #x) occurs
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 309 and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. tim x i remains valid when interrupts are not enabled (time set low) and may be polled to detect trail trace identifier mismatch events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 310 register 421h, 461h, 4a1h: rttb, tu #2 in tug2 #1 to tug2 #7, tim interrupt bit type function default bit 7 unused x bit 6 r tim7i 0 bit 5 r tim6i 0 bit 4 r tim5i 0 bit 3 r tim4i 0 bit 2 r tim3i 0 bit 1 r tim2i 0 bit 0 r tim1i 0 this register is used to identify and acknowledge trail trace identifier mismatch interrupts for the tributaries tu #2 in tug2 #1 to tug2 #7. tim1i-tim7i: the tim1i to tim7i bits identify the source of trail trace identifier mismatch interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) mode, the associated tim x i bit is unused and will return a logic 0 when read. when operational, the tim1i to tim7i bits report and acknowledge tim interrupt of tu #2 in tug2 #1 to tug2 #7, respectively. interrupts are generated upon change of identifier mismatch state. an tim x i bit is set high when a trail trace identifier mismatch event on the corresponding tributary (tu #2 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. tim x i remains valid when interrupts are not enabled (time set low) and may be polled to detect trail trace identifier mismatch events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 311 register 422h, 462h, 4a2h: rttb, tu #3 in tug2 #1 to tug2 #7, tim interrupt bit type function default bit 7 unused x bit 6 r tim7i 0 bit 5 r tim6i 0 bit 4 r tim5i 0 bit 3 r tim4i 0 bit 2 r tim3i 0 bit 1 r tim2i 0 bit 0 r tim1i 0 this register is used to identify and acknowledge trail trace identifier mismatch interrupts for the tributaries tu #3 in tug2 #1 to tug2 #7. tim1i-tim7i: the tim1i to tim7i bits identify the source of trail trace identifier mismatch interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) or vt3 mode, the associated tim x i bit is unused and will return a logic 0 when read. when operational, the tim1i to tim7i bits report and acknowledge tim interrupt of tu #3 in tug2 #1 to tug2 #7, respectively. interrupts are generated upon change of identifier mismatch state. an tim x i bit is set high when a trail trace identifier mismatch event on the corresponding tributary (tu #3 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. tim x i remains valid when interrupts are not enabled (time set low) and may be polled to detect trail trace identifier mismatch events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 312 register 423h, 463h, 4a3h: rttb, tu #4 in tug2 #1 to tug2 #7, tim interrupt bit type function default bit 7 unused x bit 6 r tim7i 0 bit 5 r tim6i 0 bit 4 r tim5i 0 bit 3 r tim4i 0 bit 2 r tim3i 0 bit 1 r tim2i 0 bit 0 r tim1i 0 this register is used to identify and acknowledge trail trace identifier mismatch interrupts for the tributaries tu #4 in tug2 #1 to tug2 #7. tim1i-tim7i: the tim1i to tim7i bits identify the source of trail trace identifier mismatch interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6), vt3 or tu12 (vt2) mode, the associated tim x i bit is unused and will return a logic 0 when read. when operational, the tim1i to tim7i bits report and acknowledge tim interrupt of tu #4 in tug2 #1 to tug2 #7, respectively. interrupts are generated upon change of identifier mismatch state. an tim x i bit is set high when a trail trace identifier mismatch event on the corresponding tributary (tu #4 in tug2 #x) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. tim x i remains valid when interrupts are not enabled (time set low) and may be polled to detect trail trace identifier mismatch events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 313 register 424h, 464h, 4a4h: rttb, tu3 or tu #1 in tug2 #1 to tug2 #7, tiu interrupt bit type function default bit 7 unused x bit 6 r tiu7i 0 bit 5 r tiu6i 0 bit 4 r tiu5i 0 bit 3 r tiu4i 0 bit 2 r tiu3i 0 bit 1 r tiu2i 0 bit 0 r tiu1i 0 this register is used to identify and acknowledge trail trace identifier unstable interrupts for the tributaries tu #1 in tug2 #1 to tug2 #7. it is also used to identify and acknowledge tu3 trail trace identifier unstable interrupts. tiu1i: the tiu1i bit identifies the source of trail trace identifier unstable interrupts. in tu3 mode, the tiu1i bit reports and acknowledges tiu interrupt of the tu3 trail trace identifier. out of tu3 mode, tiu1i bit reports and acknowledges tiu interrupt of tu #1 in tug2 #1. interrupts are generated upon change of identifier unstable state. the tiu1i bit is set high when a trail trace identifier unstable event and is cleared immediately following a read of this register, which also acknowledges and clears the interrupt. the tiu1i bit remains valid when interrupts are not enabled (tiue set low) and may be polled to detect trail trace identifier unstable events. tiu2i-tiu7i: the tiu2i to tiu7i bits identify the source of trail trace identifier unstable interrupts. tiu2i to tiu7i bits report and acknowledge tiu interrupt of tu #1 in tug2 #2 to tug2 #7, respectively. interrupts are generated upon change of identifier unstable state. an tiu x i bit is set high when a trail trace identifier unstable event on the corresponding tributary (tu #1 in tug2 # x ) occurs and
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 314 are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. tiu x i remains valid when interrupts are not enabled (tiue set low) and may be polled to detect trail trace identifier unstable events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 315 register 425h, 465h, 4a5h: rttb, tu #2 in tug2 #1 to tug2 #7, tiu interrupt bit type function default bit 7 unused x bit 6 r tiu7i 0 bit 5 r tiu6i 0 bit 4 r tiu5i 0 bit 3 r tiu4i 0 bit 2 r tiu3i 0 bit 1 r tiu2i 0 bit 0 r tiu1i 0 this register is used to identify and acknowledge trail trace identifier unstable interrupts for the tributaries tu #2 in tug2 #1 to tug2 #7. tiu1i-tiu7i: the tiu1i to tiu7i bits identify the source of trail trace identifier unstable interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) mode, the associated tiu x i bit is unused and will return a logic 0 when read. when operational, the tiu1i to tiu7i bits report and acknowledge tiu interrupt of tu #2 in tug2 #1 to tug2 #7, respectively. interrupts are generated upon change of identifier unstable state. an tiu x i bit is set high when a trail trace identifier unstable event on the corresponding tributary (tu #2 in tug2 # x ) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. tiu x i remains valid when interrupts are not enabled (tiue set low) and may be polled to detect trail trace identifier unstable events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 316 register 426h, 466h, 4a6h: rttb, tu #3 in tug2 #1 to tug2 #7, tiu interrupt bit type function default bit 7 unused x bit 6 r tiu7i 0 bit 5 r tiu6i 0 bit 4 r tiu5i 0 bit 3 r tiu4i 0 bit 2 r tiu3i 0 bit 1 r tiu2i 0 bit 0 r tiu1i 0 this register is used to identify and acknowledge trail trace identifier unstable interrupts for the tributaries tu #3 in tug2 #1 to tug2 #7. tiu1i-tiu7i: the tiu1i to tiu7i bits identify the source of trail trace identifier unstable interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6) or vt3 mode, the associated tiu x i bit is unused and will return a logic 0 when read. when operational, the tiu1i to tiu7i bits report and acknowledge tiu interrupt of tu #3 in tug2 #1 to tug2 #7, respectively. interrupts are generated upon change of identifier unstable state. an tiu x i bit is set high when a trail trace identifier unstable event on the corresponding tributary (tu #3 in tug2 # x ) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. tiu x i remains valid when interrupts are not enabled (tiue set low) and may be polled to detect trail trace identifier unstable events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 317 register 427h, 467h, 4a7h: rttb, tu #4 in tug2 #1 to tug2 #7, tiu interrupt bit type function default bit 7 unused x bit 6 r tiu7i 0 bit 5 r tiu6i 0 bit 4 r tiu5i 0 bit 3 r tiu4i 0 bit 2 r tiu3i 0 bit 1 r tiu2i 0 bit 0 r tiu1i 0 this register is used to identify and acknowledge trail trace identifier unstable interrupts for the tributaries tu #4 in tug2 #1 to tug2 #7. tiu1i-tiu7i: the tiu1i to tiu7i bits identify the source of trail trace identifier unstable interrupts. in tu3 mode, these bits are unused and will return a logic 0 when read. when the corresponding tug2 tributary group is configured for tu2 (vt6), vt3 or tu12 (vt2) mode, the associated tim x i bit is unused and will return a logic 0 when read. when operational, the tiu1i to tiu7i bits report and acknowledge tiu interrupt of tu #4 in tug2 #1 to tug2 #7, respectively. interrupts are generated upon change of identifier unstable state. an tiu x i bit is set high when a trail trace identifier unstable event on the corresponding tributary (tu #4 in tug2 # x ) occurs and are cleared immediately following a read of this register, which also acknowledges and clears the interrupt. tiu x i remains valid when interrupts are not enabled (tiue set low) and may be polled to detect trail trace identifier unstable events.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 318 register 428h, 468h, 4a8h: rttb, tiu threshold bit type function default bit 7 r/w tiu64[3] 0 bit 6 r/w tiu64[2] 1 bit 5 r/w tiu64[1] 1 bit 4 r/w tiu64[0] 1 bit 3 r/w tiu16[3] 0 bit 2 r/w tiu16[2] 1 bit 1 r/w tiu16[1] 1 bit 0 r/w tiu16[0] 1 this register contains threshold for declaration of the trail trace identifier unstable alarm (tiu) for 16-byte and 64-byte tributary path trace messages. tiu16[3:0]: the 16-byte message trail trace identifier unstable threshold bits (tiu16[3:0]) controls level in the unstable counter at which to declare tiu. when algo2 is set low, each time a received message differs from the previous message, the unstable counter is incremented. when the count exceeds tiu16, the tiu alarm is declared. when algo2 is set high, a message that differs from the previous initiates the unstable counter to count once per message. when the count exceeds tiu16, the tiu alarm is declared. tiu is negated and the unstable counter cleared when a consistent message is repeated three or five times, as controlled by the per5 bit, to become the accepted message. tiu64[3:0]: the 64-byte message trail trace identifier unstable threshold bits (tiu64[3:0]) controls level in the unstable counter at which to declare tiu. when algo2 is set low, each time a received message differs from the previous message, the unstable counter is incremented. when the count exceeds tiu64, the tiu alarm is declared. when algo2 is set high, a message that differs from the previous initiates the unstable counter to count once per message. when the count exceeds tiu64, the tiu alarm is declared. tiu is negated and the
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 319 unstable counter cleared when a consistent message is repeated three or five times, as controlled by the per5 bit, to become the accepted message.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 320 register 429h, 469h, 4a9h: rttb, indirect tributary select bit type function default bit 7 r/w cpage 0 bit 6 unused x bit 5 unused x bit 4 r/w tug2[2] 0 bit 3 r/w tug2[1] 0 bit 2 r/w tug2[0] 0 bit 1 r/w tu[1] 0 bit 0 r/w tu[0] 0 this register contains the identity of the tributary buffer to be accessed in an indirect read or write operation. tu[1:0]: the tributary unit address bits (tu[1:0]) identifies the tributary within the tributary unit group which is identified by the tug2[2:0] bits. the combination of tug2[2:0] and tu[1:0] identifies the tributary buffer to be accessed indirectly. tug2[2:0]: the tributary unit group address bits (tug2[2:0]) identifies the tributary unit group. the combination of tug2[2:0] and tu[1:0] identifies the tributary buffer to be accessed indirectly. cpage: the capture page control bit (cpage) selects between accessing the capture page and the expected page of the tributary buffer. when cpage is set high, the indirect register access is targeted at the capture page. reading from the capture page returns the most recent tributary path trace message received from the incoming stream. no de-bouncing is provided. when cpage is set low, the indirect register access is targeted at the expected page. an expected
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 321 trace message can be provisioned by writing to the expected page. both the capture and expected pages may be read from or written to.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 322 register 42ah, 46ah, 4aah: rttb, indirect address select bit type function default bit 7 r busy 0 bit 6 r/w rwb 0 bit 5 r/w a[5] 0 bit 4 r/w a[4] 0 bit 3 r/w a[3] 0 bit 2 r/w a[2] 0 bit 1 r/w a[1] 0 bit 0 r/w a[0] 0 this register provides the byte address within the tributary buffer addressed by the indirect tributary select register. writing to this register triggers an indirect register access.. a[5:0]: the indirect address bits (a[5:0]) index into the receive and expected pages of the tributary buffers. rwb: the indirect access control bit (rwb) selects between a read and write operation into the tributary buffers. writing a logic zero to rwb triggers an indirect write operation. the tributary buffer is selected by the tug2[2:0] and tu[1:0] bits in the indirect tributary register. selection between the capture page and the expected page is controlled by the cpage bit also in the indirect tributary register. bytes within the tributary buffer are indexed by a[5:0]. data to be written is taken from d[7:0] of the indirect data register. writing a logic one to rwb triggers an indirect read operation. tributary buffer, page, and byte addressing is the same as in an indirect write operation. the data read can be found in d[7:0] of the indirect data register.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 323 busy: the indirect access status bit (busy) reports the progress of an indirect access. busy is set high when this register is written to trigger an indirect access and will stay high until the access is complete. at which point, busy will be set low. this register should be polled to determine when data from an indirect read operation is available in the indirect data register or to determine when a new indirect write operation may commence.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 324 register 42bh, 46bh, 4abh: rttb, indirect data select bit type function default bit 7 r/w d[7] 0 bit 6 r/w d[6] 0 bit 5 r/w d[5] 0 bit 4 r/w d[4] 0 bit 3 r/w d[3] 0 bit 2 r/w d[2] 0 bit 1 r/w d[1] 0 bit 0 r/w d[0] 0 this register contains the data read from a tributary buffer after an indirect read operation or the data to be inserted into a tributary buffer in an indirect write operation. d[7:0]: the indirect data bits (d[7:0]) reports the data read from a tributary buffer after an indirect read operation has complete. data to be written to a tributary buffer in an indirect write operation must be set up in this register before triggering the write. data in this register reflects the value written until the completion of a subsequent indirect read operation.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 325 12 test features description simultaneously asserting (low) the csb, rdb and wrb inputs when the mbeb input is negated (high), causes all output pins and the data bus to be held in a high-impedance state. this test feature may be used for board testing. test mode registers are used to apply test vectors during production testing of the tupp+622. test mode registers (as opposed to normal mode registers) are selected when a[13] is high. test mode registers may also be used for board testing. when all of the tributary payload processors within the tupp+622 are placed in test mode 0, device inputs may be read and device outputs may be forced via the microprocessor interface (refer to the section "test mode 0" for details). table 3 - test mode register memory map stp #1 stp #2 stp #3 stp #4 register 0000h- 07ffh 0800h- 0fffh 1000h- 17ffh 1800h- 1fffh normal mode registers 2000h master test register 2001h stp select register 2002h 2802h 3002h 3802h i/o test register 1 2003h 2803h 3003h 3803h i/o test register 2 2004h 2804h 3004h 3804h i/o test register 3 2005h 2805h 3005h 3805h i/o test register 4 2006h 2806h 3006h 3806h i/o test register 5 2006h- 201fh 2806h- 281fh 3006h- 301fh 3806h- 381fh reserved 2020h 2820h 3020h 3820h vtpp #1 test register 0 2021h 2821h 3021h 3821h vtpp #1 test register 2 2022h 2822h 3022h 3822h vtpp #1 test register 4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 326 stp #1 stp #2 stp #3 stp #4 register 2023h- 203fh 2823h- 283fh 3023h- 303fh 3823h- 383fh reserved 20a0h 28a0h 30a0h 38a0h vtpp #1 test register 1 20a1h 28a1h 30a1h 38a1h vtpp #1 test register 3 20a2h 28a2h 30a2h 38a2h vtpp #1 test register 5 20a3h- 20bfh 28a3h- 28bfh 30a3h- 30bfh 38a3h- 38bfh reserved 2040h 2840h 3040h 3840h vtpp #2 test register 0 2041h 2841h 3041h 3841h vtpp #2 test register 2 2042h 2842h 3042h 3842h vtpp #2 test register 4 2043h- 205fh 2843h- 285fh 3043h- 305fh 3843h- 385fh reserved 20c0h 28c0h 30c0h 38c0h vtpp #2 test register 1 20c1h 28c1h 30c1h 38c1h vtpp #2 test register 3 20c2h 28c2h 30c2h 38c2h vtpp #2 test register 5 20c3h- 20dfh 28c3h- 28dfh 30c3h- 30dfh 38c3h- 38dfh reserved 2060h 2860h 3060h 3860h vtpp #3 test register 0 2061h 2861h 3061h 3861h vtpp #3 test register 2 2062h 2862h 3062h 3862h vtpp #3 test register 4 2063h- 207fh 2863h- 287fh 3063h- 307fh 3863h- 387fh reserved 20e0h 28e0h 30e0h 38e0h vtpp #3 test register 1 20e1h 28e1h 30e1h 38e1h vtpp #3 test register 3 20e2h 28e2h 30e2h 38e2h vtpp #3 test register 5 20e3h- 20ffh 28e3h- 28ffh 30e3h- 30ffh 38e3h- 38ffh reserved
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 327 stp #1 stp #2 stp #3 stp #4 register 2100h 2900h 3100h 3900h rtop #1 test register 0 2101h 2901h 3101h 3901h rtop #1 test register 1 2102h 2902h 3102h 3902h rtop #1 test register 2 2103h 2903h 3103h 3903h rtop #1 test register 3 2104h 2904h 3104h 3904h rtop #1 test register 4 2105h 2905h 3105h 3905h rtop #1 test register 5 2106h 2906h 3106h 3906h rtop #1 test register 6 2107h 2907h 3107h 3907h rtop #1 test register 7 2108h 2908h 3108h 3908h rtop #1 test register 8 2109h 2909h 3109h 3909h rtop #1 test register 9 210ah 290ah 310ah 390ah rtop #1 test register 10 210bh 290bh 310bh 390bh rtop #1 test register 11 210ch 290ch 310ch 390ch rtop #1 test register 12 210dh 290dh 310dh 390dh rtop #1 test register 13 210eh 290eh 310eh 390eh rtop #1 test register 14 210fh 290fh 310fh 390fh rtop #1 test register 15 2110h- 21ffh 2910h- 29ffh 3110h- 31ffh 3910h- 39ffh reserved 2200h ? 220fh 2a00h - 2a0fh 3200h - 320fh 3a00h - 3a0fh rtop #2 test register 0 - 15 2210h- 22ffh 2a10h- 2affh 3210h- 32ffh 3a10h- 3affh reserved 2300h ? 230fh 2b00h - 2b0fh 3300h - 330fh 3b00h - 3b0fh rtop #3 test register 0 - 15 2310h- 23ffh 2b10h- 2bffh 3310h- 33ffh 3b10h- 3bffh reserved 2400h 2c00h 3400h 3c00h rttb #1 test register 0
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 328 stp #1 stp #2 stp #3 stp #4 register 2401h 2c01h 3401h 3c01h rttb #1 test register 1 2402h 2c02h 3402h 3c02h rttb #1 test register 2 2403h 2c03h 3403h 3c03h rttb #1 test register 3 2404h- 243fh 2c04h- 2c3fh 3404h- 343fh 3c04h- 3c3fh reserved 2440h - 2443h 2c40h - 2c43h 3440h - 3443h 3c40h - 3c43h rttb #2 test register 0 - 3 2444h- 247fh 2c44h- 2c7fh 3444h- 347fh 3c44h- 3c7fh reserved 2480h - 2483h 2c80h - 2c83h 3480h - 3483h 3c80h - 3c83h rttb #3 test register 0 - 3 2484h- 27ffh 2c84h- 2fffh 3484h- 37ffh 3c84h- 3fffh reserved notes on test mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic 0. reading back unused bits can produce either a logic 1 or a logic 0; hence unused register bits should be masked off by software when read. 2. writeable test mode register bits are not initialized upon reset unless otherwise noted.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 329 register 2000h: master test bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 w pmctst x bit 3 w mototst x bit 2 r/w iotst 0 bit 1 w hizdata x bit 0 r/w hizio 0 this register is used to enable tupp+622 test features. all bits, except pmctst, are reset to zero by a reset of the tupp+622. hizio,hizdata: the hizio and hizdata bits control the tri-state modes of the tupp+622 . while the hizio bit is a logic 1, all output pins of the tupp+622 except the data bus are held in a high-impedance state. the microprocessor interface is still active. while the hizdata bit is a logic 1, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. iotst: the iotst bit is used to allow normal microprocessor access to the test registers and control the test mode in each tsb block in the tupp+622 for board level testing. when iotst is a logic 1, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequently the device outputs (refer to the "test mode 0 details" in the "test features" section). mototst: the mototst bit is used to test the decoding of the rdb_e and wrb_rwb control signals when mbeb is logic 0.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 330 pmctst: the pmctst bit is used to configure the tupp+622 for pmc's manufacturing tests. when pmctst is set to logic 1, the tupp+622 microprocessor port becomes the test access port used to run the pmc "canned" manufacturing test vectors. the pmctst bit is logically "or'ed" with the iotst bit, and can only be cleared by setting csb to logic 1.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 331 register 2001h: stp select bit type function default bit 7 w stpsel[1] x bit 6 w stpsel[0] x bit 5 w ssel[1] x bit 4 w ssel[0] x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x this register is used to select the stm-1 (sts-3) tributary processor (stp) and the vtpp, rtop, rttb slice when the pmc's manufacturing test mode for the tupp+622 is enabled. ssel[1:0]: the test mode (tsb) slice selection bits (ssel[1:0]) control cbi access to the vtpp[3:1], rtop[3:1] and rttb[3:1] of a selected stp when pmctst is set high. when ssel is set to 'b00, the selection among the tsbs in stp #1 - #4 is directly controlled by the address bus (a[13:0]). when ssel is set to the three higher values, tsb selection is a combination of the address bus, the stpsel values and the ssel values. the stp is selected by the stpsel values. the selection among the vtpp, rtop and rttb tsbs is made by setting the address to the address range of vtpp #1, rtop #1 and rttb #1, respectively. the choice of tsb slice #1, #2 and #3 is controlled by writing 'b01, 'b10 and 'b11, respectively, to the ssel[1:0] bits. the ssel[1:0] bits are cleared by setting csb to logic 1. stpsel[1:0]: the test mode stp selection bits (stpsel[1:0]) control cbi access to the stp #1, #2, #3 and #4 when pmctst is set high and the ssel[1:0] bits are set to ?b01, ?b10 or ?b11. the choice of stp #1, #2, #3 or #4 is controlled by
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 332 writing 'b00, 'b01, 'b10 or ?b11 to the stpsel[1:0] bits, respectively. the stpsel[1:0] bits are cleared by setting csb to logic 1. 12.1 i/o test mode in i/o test mode (iotst in master test register set high), the tupp+622 allows the logic levels on the device inputs to be read through the microprocessor interface, and allows the device outputs to be forced to either logic level through the microprocessor interface.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 333 test register 2002h: (write in i/o test mode) bit type function default bit 7 w od[7] x bit 6 w od[6] x bit 5 w od[5] x bit 4 w od[4] x bit 3 w od[3] x bit 2 w od[2] x bit 1 w od[1] x bit 0 w od[0] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 334 test register 2003h: (write in i/o test mode) bit type function default bit 7 w odp[1] x bit 6 w otpl[1] x bit 5 w otv5[1] x bit 4 w ais[1] x bit 3 w idle[1] x bit 2 w oc1j1v1[1] x bit 1 w opl[1] x bit 0 w intb x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 335 test register 2004h: (write in i/o test mode) bit type function default bit 7 unused x bit 6 unused x bit 5 w poh[3] x bit 4 w poh[2] x bit 3 w poh[1] x bit 2 w pohfp[3] x bit 1 w pohfp[2] x bit 0 w pohfp[1] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 336 test register 2005h: (write in i/o test mode) bit type function default bit 7 unused x bit 6 unused x bit 5 w pohen[3] x bit 4 w pohen[2] x bit 3 w pohen[1] x bit 2 unused x bit 1 unused x bit 0 w pohck x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 337 test register 2006h: (write in i/o test mode) bit type function default bit 7 w cout[1] x bit 6 w rad[1] x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 w tpoh[1] x bit 1 w gsclk[1] x bit 0 w gsclk[0] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 338 test register 2802h: (write in i/o test mode) bit type function default bit 7 w od[15] x bit 6 w od[14] x bit 5 w od[13] x bit 4 w od[12] x bit 3 w od[11] x bit 2 w od[10] x bit 1 w od[9] x bit 0 w od[8] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 339 test register 2803h: (write in i/o test mode) bit type function default bit 7 w odp[2] x bit 6 w otpl[2] x bit 5 w otv5[2] x bit 4 w ais[2] x bit 3 w idle[2] x bit 2 w oc1j1v1[2] x bit 1 w opl[2] x bit 0 unused x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 340 test register 2804h: (write in i/o test mode) bit type function default bit 7 unused x bit 6 unused x bit 5 w poh[6] x bit 4 w poh[5] x bit 3 w poh[4] x bit 2 w pohfp[6] x bit 1 w pohfp[5] x bit 0 w pohfp[4] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 341 test register 2805h: (write in i/o test mode) bit type function default bit 7 unused x bit 6 unused x bit 5 w pohen[6] x bit 4 w pohen[5] x bit 3 w pohen[4] x bit 2 unused x bit 1 unused x bit 0 unused x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 342 test register 2806h: (write in i/o test mode) bit type function default bit 7 w cout[2] x bit 6 w rad[2] x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 w tpoh[2] x bit 1 unused x bit 0 unused x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 343 test register 3002h: (write in i/o test mode) bit type function default bit 7 w od[23] x bit 6 w od[22] x bit 5 w od[21] x bit 4 w od[20] x bit 3 w od[19] x bit 2 w od[18] x bit 1 w od[17] x bit 0 w od[16] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 344 test register 3003h: (write in i/o test mode) bit type function default bit 7 w odp[3] x bit 6 w otpl[3] x bit 5 w otv5[3] x bit 4 w ais[3] x bit 3 w idle[3] x bit 2 w oc1j1v1[3] x bit 1 w opl[3] x bit 0 unused x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 345 test register 3004h: (write in i/o test mode) bit type function default bit 7 unused x bit 6 unused x bit 5 w poh[9] x bit 4 w poh[8] x bit 3 w poh[7] x bit 2 w pohfp[9] x bit 1 w pohfp[8] x bit 0 w pohfp[7] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 346 test register 3005h: (write in i/o test mode) bit type function default bit 7 unused x bit 6 unused x bit 5 w pohen[9] x bit 4 w pohen[8] x bit 3 w pohen[7] x bit 2 unused x bit 1 unused x bit 0 unused x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 347 test register 3006h: (write in i/o test mode) bit type function default bit 7 w cout[3] x bit 6 w rad[3] x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 tpoh[3] x bit 1 unused x bit 0 unused x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 348 test register 3802h: (write in i/o test mode) bit type function default bit 7 w od[31] x bit 6 w od[30] x bit 5 w od[29] x bit 4 w od[28] x bit 3 w od[27] x bit 2 w od[26] x bit 1 w od[25] x bit 0 w od[24] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 349 test register 3803h: (write in i/o test mode) bit type function default bit 7 w odp[4] x bit 6 w otpl[4] x bit 5 w otv5[4] x bit 4 w ais[4] x bit 3 w idle[4] x bit 2 w oc1j1v1[4] x bit 1 w opl[4] x bit 0 unused x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 350 test register 3804h: (write in i/o test mode) bit type function default bit 7 unused x bit 6 unused x bit 5 w poh[12] x bit 4 w poh[11] x bit 3 w poh[10] x bit 2 w pohfp[12] x bit 1 w pohfp[11] x bit 0 w pohfp[10] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 351 test register 3805h: (write in i/o test mode) bit type function default bit 7 unused x bit 6 unused x bit 5 w pohen[12] x bit 4 w pohen[11] x bit 3 w pohen[10] x bit 2 unused x bit 1 unused x bit 0 unused x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 352 test register 3806h: (write in i/o test mode) bit type function default bit 7 w cout[4] x bit 6 w rad[4] x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 w tpoh[4] x bit 1 unused x bit 0 unused x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 353 test register 2002h: (read in i/o test mode) bit type function default bit 7 r id[7] x bit 6 r id[6] x bit 5 r id[5] x bit 4 r id[4] x bit 3 r id[3] x bit 2 r id[2] x bit 1 r id[1] x bit 0 r id[0] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 354 test register 2003h: (read in i/o test mode) bit type function default bit 7 r reserved x bit 6 r ic1j1[1] x bit 5 r ipl[1] x bit 4 r itmf[1] x bit 3 r idp[1] x bit 2 r otmf[1] x bit 1 r gsclk_fp x bit 0 r reserved x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 355 test register 2004h: (read in i/o test mode) bit type function default bit 7 r hsclk x bit 6 r ihsmodeb x bit 5 r ohsmodeb x bit 4 r itv5[1] x bit 3 r itpl[1] x bit 2 r iais[1] x bit 1 r reserved x bit 0 r reserved x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 356 test register 2802h: (read in i/o test mode) bit type function default bit 7 r id[15] x bit 6 r id[14] x bit 5 r id[13] x bit 4 r id[12] x bit 3 r id[11] x bit 2 r id[10] x bit 1 r id[9] x bit 0 r id[8] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 357 test register 2803h: (read in i/o test mode) bit type function default bit 7 r reserved x bit 6 r ic1j1[2] x bit 5 r ipl[2] x bit 4 r itmf[2] x bit 3 r idp[2] x bit 2 r otmf[2] x bit 1 r reserved x bit 0 r reserved x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 358 test register 2804h: (read in i/o test mode) bit type function default bit 7 r reserved x bit 6 r reserved x bit 5 r reserved x bit 4 r itv5[2] x bit 3 r itpl[2] x bit 2 r iais[2] x bit 1 r reserved x bit 0 r reserved x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 359 test register 3002h: (read in i/o test mode) bit type function default bit 7 r id[23] x bit 6 r id[22] x bit 5 r id[21] x bit 4 r id[20] x bit 3 r id[19] x bit 2 r id[18] x bit 1 r id[17] x bit 0 r id[16] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 360 test register 3003h: (read in i/o test mode) bit type function default bit 7 r reserved x bit 6 r ic1j1[3] x bit 5 r ipl[3] x bit 4 r itmf[3] x bit 3 r idp[3] x bit 2 r otmf[3] x bit 1 r reserved x bit 0 r reserved x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 361 test register 3004h: (read in i/o test mode) bit type function default bit 7 r reserved x bit 6 r reserved x bit 5 r reserved x bit 4 r itv5[3] x bit 3 r itpl[3] x bit 2 r iais[3] x bit 1 r reserved x bit 0 r reserved x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 362 test register 3802h: (read in i/o test mode) bit type function default bit 7 r id[31] x bit 6 r id[30] x bit 5 r id[29] x bit 4 r id[28] x bit 3 r id[27] x bit 2 r id[26] x bit 1 r id[25] x bit 0 r id[24] x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 363 test register 3803h: (read in i/o test mode) bit type function default bit 7 r reserved x bit 6 r ic1j1[4] x bit 5 r ipl[4] x bit 4 r itmf[4] x bit 3 r idp[4] x bit 2 r otmf[4] x bit 1 r reserved x bit 0 r reserved x
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 364 test register 3804h: (read in i/o test mode) bit type function default bit 7 r reserved x bit 6 r reserved x bit 5 r reserved x bit 4 r itv5[4] x bit 3 r itpl[4] x bit 2 r iais[4] x bit 1 r reserved x bit 0 r reserved x 12.2 jtag test port the tupp+622 jtag test access port (tap) allows access to the tap controller and the 4 tap registers: instruction, bypass, device identification and boundary scan. using the tap, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. for more details on the jtag port, please refer to the operation section. table 4 - instruction register (length ? 3 bits) instructions selected register instruction codes, ir[2:0] extest boundary scan 000 idcode identification 001 sample boundary scan 010 bypass bypass 011 bypass bypass 100 stctest boundary scan 101 bypass bypass 110 bypass bypass 111
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 365 table 5 -identification register length 32 bits version number 1h part number 5363h manufacturer's identification code 0cdh device identification 153630cdh table 6 boundary scan register (length ? 218 bits) order # pin # pin name pin type id value 0 hiz output enable 1 d3 oc1j1v1[1] output 2 e4 opl[1] output 3 c1 od[0] output 4 d2 od[1] output 5 e3 od[2] output 6 d1 od[3] output 7 e2 od[4] output 8 f3 od[5] output 9 g4 od[6] output 10 e1 od[7] output 11 f2 odp[1] output 12 g3 otv5[1] output 13 h4 otpl[1] output 14 g1 ais[1] output 15 h3 idle[1] output 16 h2 tpoh[1] output 17 j3 cout[1] output 18 j2 otmf[1] input 19 k4 hsclk input
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 366 order # pin # pin name pin type id value 20 j1 gsclk_fp input 21 k3 rad[1] output 22 k1 pohfp[1] output 23 l4 poh[1] output 24 l3 pohen[1] output 25 l2 pohck output 26 l1 pohfp[2] output 27 m3 poh[2] output 28 m2 pohen[2] output 29 n1 pohfp[3] output 30 n3 gsclk[0] output 31 n4 gsclk[1] output 32 p1 sclk input 33 p2 poh[3] output 34 p3 pohen[3] output 35 r1 ic1j1[1] input 36 p4 ipl[1] input 37 r2 id[0] input 38 r3 id[1] input 39 t2 id[2] input 40 u1 id[3] input 41 t3 id[4] input 42 t4 id[5] input 43 u3 id[6] input 44 v2 id[7] input 45 w1 idp[1] input 46 u4 itmf[1] input
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 367 order # pin # pin name pin type id value 47 v3 itv5[1] input 48 w2 itpl[1] input 49 y1 iais[1] input 50 w3 ihsmodeb input 51 y2 ohsmodeb input 52 aa1 ic1j1[4] input 53 w4 ipl[4] input 54 y3 id[24] input 55 aa4 id[25] input 56 y5 id[26] input 57 ac3 id[27] input 58 ab4 id[28] input 59 aa5 id[29] input 60 ac4 id[30] input 61 ab5 id[31] input 62 aa6 idp[4] input 63 ac5 itmf[4] input 64 ab6 itv5[4] input 65 aa7 itpl[4] input 66 y8 iais[4] input 67 ac7 rad[4] output 68 aa8 pohfp[10] output 69 ab8 poh[10] output 70 aa9 pohen[10] output 71 ab9 pohfp[11] output 72 y10 poh[11] output 73 ac9 pohen[11] output
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 368 order # pin # pin name pin type id value 74 aa10 pohfp[12] output 75 ac10 poh[12] output 76 y11 pohen[12] output 77 aa11 otmf[4] input 78 ab11 oc1j1v1[4] output 79 ac11 opl[4] output 80 aa12 od[24] output 81 ab12 od[25] output 82 ac13 od[26] output 83 aa13 od[27] output 84 y13 od[28] output 85 ac14 od[29] output 86 ab14 od[30] output 87 aa14 od[31] output 88 ac15 odp[4] output 89 y14 otv5[4] output 90 ab15 otpl[4] output 91 aa15 ais[4] output 92 ab16 idle[4] output 93 ac17 tpoh[4] output 94 aa16 cout[4] output 95 aa17 ic1j1[3] input 96 ab18 ipl[3] input 97 ac19 id[16] input 98 y17 id[17] input 99 aa18 id[18] input 100 ab19 id[19] input
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 369 order # pin # pin name pin type id value 101 ac20 id[20] input 102 aa19 id[21] input 103 ab20 id[22] input 104 ac21 id[23] input 105 y19 idp[3] input 106 aa20 itmf[3] input 107 y21 itv5[3] input 108 w20 itpl[3] input 109 aa23 iais[3] input 110 y22 pohen [9] output 111 w21 poh[9] output 112 y23 pohfp [9] output 113 w22 pohen [8] output 114 v21 poh[8] output 115 u20 pohfp [8] output 116 w23 pohen [7] output 117 v22 poh[7] output 118 u21 pohfp [7] output 119 t20 rad[3] output 120 u23 cout[3] output 121 t21 tpoh[3] output 122 t22 idle[3] output 123 r21 ais[3] output 124 r22 otpl[3] output 125 p20 otv5[3] output 126 r23 odp[3] output 127 p21 od[23] output
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 370 order # pin # pin name pin type id value 128 p22 od[22] output 129 p23 od[21] output 130 n20 od[20] output 131 n21 od[19] output 132 n23 od[18] output 133 m21 od[17] output 134 m22 od[16] output 135 l23 opl[3] output 136 l22 oc1j1v1 [3] output 137 l21 otmf[3] input 138 l20 cout[2] output 139 k23 tpoh[2] output 140 k22 idle[2] output 141 k21 ais[2] output 142 j23 otpl[2] output 143 k20 otv5[2] output 144 j21 odp[2] output 145 h22 od[15] output 146 g23 od[14] output 147 h21 od[13] output 148 g22 od[12] output 149 h20 od[11] output 150 g21 od[10] output 151 f22 od[9] output 152 e23 od[8] output 153 g20 opl[2] output 154 f21 oc1j1v1 [2] output
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 371 order # pin # pin name pin type id value 155 d23 otmf[2] input 156 e21 pohen [6] output 157 d22 poh[6] output 158 c23 pohfp [6] output 159 e20 pohen [5] output 160 d21 poh[5] output 161 c20 pohfp [5] output 162 d19 pohen [4] output 163 a21 poh[4] output 164 b20 pohfp [4] output 165 c19 rad[2] output 166 a20 iais[2] input 167 b19 itpl[2] input 168 c18 itv5[2] input 169 c14 intb output 170 oenb[7] oe 171 a14 d[7] i/o 172 oenb[6] oe 173 d13 d[6] i/o 174 oenb[5] oe 175 c13 d[5] i/o 176 oenb[4] oe 177 b13 d[4] i/o 178 oenb[3] oe 179 a13 d[3] i/o 180 oenb[2] oe 181 c12 d[2] i/o
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 372 order # pin # pin name pin type id value 182 oenb[1] oe 183 b12 d[1] i/o 184 oenb[0] oe 185 a11 d[0] i/o 186 d17 itmf[2] input 1 187 a19 idp[2] input 0 188 b18 id[15] input 1 189 c17 id[14] input 1 190 d16 id[13] input 0 191 a17 id[12] input 0 192 c16 id[11] input 1 193 b16 id[10] input 1 194 c15 id[9] input 0 195 b15 id[8] input 0 196 d14 ipl[2] input 0 197 a15 ic1j1[2] input 0 198 c11 a[13] input 1 199 d11 a[12] input 1 200 a10 a[11] input 0 201 b10 a[10] input 0 202 c10 a[9] input 0 203 a9 a[8] input 1 204 d10 a[7] input 1 205 b9 a[6] input 0 206 c9 a[5] input 1 207 b8 a[4] input 1 208 a7 a[3] input 0
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 373 order # pin # pin name pin type id value 209 c8 a[2] input 0 210 b7 a[1] input 1 211 d8 a[0] input 0 212 c7 wrb input 1 213 b6 rdb input 0 214 a5 ale input 1 215 d7 rstb input 0 216 c6 mbeb input 0 217 a4 csb input 0 c5 tck tap clock b4 tdi tap input a3 tdo tap output d5 trstb tap input c4 tms tap input notes : 1. csb is the first bit of the scan chain (closest to tdi). 2. oenb[n] sets the corresponding d[n] pin to an output when set low. in the diagram of boundary scan cells, clock-dr is connected to tck when the current controller state is shift-dr or capture-dr, and unchanging otherwise. the multiplexer in the centre of the diagram selects one of four inputs, depending on the status of select lines g1 and g2. the id code bit is as listed in the table above.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 374 figure 7 - input observation cell (input, clock input) input pad d c clock-dr scan chain out input to internal logic shift-dr scan chain in 1 2 mux 1 2 1 2 1 2 i.d. code bit idcode g1 g2 figure 8 - output cell (output, clock output, output enable) d c d c g1 g2 1 2 mux g1 1 1 mux output or enab le from syst em logic scan chain in sc an ch ain out ext est output o r enable shift-dr cl ock- dr upda te- dr 1 2 1 2 1 2 idcode i.d. code bit
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 375 figure 9 - bidirectional cell (io_cell) d c d c g1 1 1 mux output from internal logic scan chain in scan chain out extest output to pin shift-dr clock-dr update-dr input from pin input to internal logic g1 1 2 mux 1 2 1 2 1 2 g2 idcode i.d. code bit figure 10 - i/o cell (i/o with oe pair) output enable from internal logic (0 = drive) input to internal logic output from internal logic scan chain in scan chain out i/o pad out_cell io_cell
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 376 13 operation 13.1 configuration options the tupp+622 consists of four independent stm-1 (sts-3) tributary processors (stp), each having the equivalent functionality of a tupp-plus (pm5362) device. stp #1, #2, #3 and #4 process the stm-1 #1, #2, #3 and #4 streams, respectively. each stp consists of three sets of tributary payload processor (vtpp), tributary path overhead processor (rtop) and tributary trace buffer (rttb). each vtpp, rtop and rttb set deals with the portion of the sonet frame that corresponds to an sts-1 spe. equivalently, each vtpp, rtop and rttb set deals with the portion of the sdh frame that corresponds to a vc3 together with the 2 columns of fixed stuff that are added when mapping a vc3 into an au3. by coordinating the operation of the three vtpps, rtops and rttbs in an stp, they can process the portion of an sdh frame that corresponds to a vc4. the coordination that may be required between the three vtpps relates to the j1 byte marker and the encoding of the tributary multiframe into the h4 byte. when processing a vc4 that carries three tug3s, the alignment provided by the j1 byte marker and the h4 byte of the vc4 must be distributed to all vtpps, rtops and rttbs in an stp. when processing sts-1 spes, or equivalently, vc3s carried within au3s, each vtpp, rtop and rttb set receives its own j1 byte marker and h4 byte. coordination is accomplished as follows: the tributary multiframe alignment that is detected by vtpp #1 is distributed to the two other vtpps which do not receive valid h4 bytes. in addition, the input demultiplexer will stretch the pulse captured on the ic1j1 input for the corresponding stm-1 stream that marks the vc4 j1 byte so that it marks the next two bytes. during the demultiplexing process this effectively feeds a "j1" marker to the two "slaved" vtpps. the modes of operation of the tupp+622 are summarized as follows: sts-1 mode: this is default. each sts-1 in an stm-1 stream is assumed to carry seven vt groups, each of which can be independently configured to carry vt1.5s, vt2s, vt3s, or vt6s. the associated ic1j1 input is expected to mark the j1 byte of each sts-1 spe and each vtpp detects the tributary multiframe encoded in the unique h4 byte that it receives. au3 mode: this is also the default, as is corresponds exactly to sts-1 mode, except for nomenclature. each au3 in an stm-1 stream is assumed to carry
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 377 seven tug2s, each of which can be independently configured to carry tu11s, tu12s, or tu2s. (the equivalent of a vt3 is allowed but there is no sdh nomenclature to describe this.) the associated ic1j1 input is expected to mark the j1 byte of each vc3 and each vtpp detects the tributary multiframe encoded in the unique h4 byte that it receives. au4 mode: this mode is enabled when the iconcat and oconcat bits of an stp are set high. in au4 mode, individual vtpps in an stp must be configured in either tug3 mode or tu3 mode. the associated ic1j1 input is expected to mark the j1 byte of the vc4. this j1 marker is stretched to provide a "j1" marker to each vtpp. vtpp #2 and vtpp#3 are slaved to the tributary multiframe indication provided by vtpp #1 as it is the only one that receives a valid h4 byte. tug3 mode: this mode is enabled when the tug3 bit is set high in a vtpp. in addition, the iconcat and oconcat bits of the stp must be set high. the tug3 processed by the vtpp is assumed to carry seven tug2s, each of which can be independently configured to carry tu11s, tu12s, or tu2s. (the equivalent of a vt3 is allowed but there is no sdh nomenclature to describe this.) when an stp in the tupp+622 is in au4 mode, each vtpp can be independently configured in tug3 or tu3 mode. tu3 mode: this mode is enabled when the tu3 bit is set high in a vtpp. in addition the iconcat and oconcat bits of the stp must be set high. the tug3 processed by the vtpp is assumed to carry a tu3. when an stp in the tupp+622 is in au4 mode, each vtpp can be independently configured in tug3 or tu3 mode. for figures in the operation and functional timing sections, transport overhead and path overhead bytes are shown for notational convenience only. in the incoming direction, except for the h4 byte, id[7:0] (id[15:8], id[23:16], id[31:24]) does not need to contain valid transport and sts/au path overhead byte values. the h4 byte must be valid only if h4 framing is enabled (itmfen=0). otherwise, it too may be invalid. however, the incoming parity must match the data supplied at all times. in the outgoing direction, tupp+622 places valid framing, sts/au pointer bytes and all-zeros data on od[7:0] (od[15:8], od[23:16], od[31:24]) for transport overhead bytes. it generates all zero bytes for the sts/au path overhead except for the h4 byte which contains leading ones and an incrementing two bit pattern. the fixed stuff bytes in the tributary mapping to the synchronous payload envelope (virtual container) are also generated as all zero
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 378 bytes. the outgoing parity reflects the data on od[7:0] (od[15:8], od[23:16], od[31:24]) at all times. 13.2 sts-1 mode an example of the placement of tributaries assumed in sts-1 mode is illustrated in figure 11. for simplicity, this figure shows the frame on the od[7:0] bus when the stm-1 (sts-3) interface mode is enabled. in this case the outgoing sts-1 spes are locked to an active offset of 522 with respect to the outgoing transport envelope frame. this particular example assumes a snapshot of the first frame of the tributary multiframe when the v1 bytes are present. this example illustrates a vt structured sts-1 spe where all vt groups are configured to carry vt1.5s. figure 11 - sonet sts-3 carrying vt1.5 within sts-1 a1 a1 a1 a2 a2 a2 c1 c1 c1 j1 j1 j1 v1 v1 v1 spe b1 - - e1 - - f1 - - b3 b3 b3 spe spe spe spe d1 - - d2 - - d3 - - c2 c2 c2 spe spe spe spe h1 h1 h1 h2 h2 h2 h3 h3 h3 g1 g1 g1 spe spe spe spe b2 b2 b2 k1 - - k2 - - f2 f2 f2 spe spe spe spe d4 - - d5 - - d6 - - h4 h4 h4 spe spe spe spe d7 - - d8 - - d9 - - z3 z3 z3 spe spe spe spe d10 - - d11 - - d12 - - z4 z4 z4 spe spe spe spe z1 - - z2 - - e2 - - z5 z5 z5 spe spe spe spe row 1 2 3 4 5 6 7 8 9 col 123456789101112131415 270 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 265 266 spe spe spe spe spe spe spe spe spe 267 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 268 269 first of 3 columns occupied by vt1.5 #1 of vt group #1 of sts-1 #1 of an sts-3 stream (column set is 13, 100, 187) last of 3 columns occupied by vt1.5 #4 of vt group #7 of sts-1 #3 of an sts-3 stream (column set is 96, 183, 270) 13.3 au3 mode an example of the placement of tributaries assumed in au3 mode is illustrated in figure 12. for simplicity, this figure shows the frame on the od[7:0] bus when the stm-1 (sts-3) interface mode is enabled. in this case the outgoing vc3s are locked to an active offset of 522 with respect to the outgoing transport envelope frame. this particular example assumes a snapshot of the last frame of the tributary multiframe when the v4 bytes are present. this example illustrates the case where the vc3s carry tug2s and all tug2s are configured to carry tu12s.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 379 figure 12 - sdh stm-1 carrying tu12 within vc3/au3 a1 a1 a1 a2 a2 a2 c1 c1 c1 v4 v4 v4 spe b1 - - e1 - - f1 - - spe spe spe spe d1 - - d2 - - d3 - - spe spe spe spe h1 h1 h1 h2 h2 h2 h3 h3 h3 spe spe spe spe b2 b2 b2 k1 - - k2 - - spe spe spe spe d4 - - d5 - - d6 - - spe spe spe spe d7 - - d8 - - d9 - - spe spe spe spe d10 - - d11 - - d12 - - spe spe spe spe z1 - - z2 - - e2 - - spe spe spe spe row 1 2 3 4 5 6 7 8 9 col 123456789101112131415 270 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 265 266 spe spe spe spe spe spe spe spe spe 267 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 268 269 first of 4 columns occupied by tu12 #1 of tug2 #1 of vc3/ au3 #1 of an stm-1 stream (column set is 13, 76,142, 208) last of 4 columns occupied by tu12 #3 of tug2 #7 of vc3/ au3 #3 of an stm-1 stream (column set is 75, 141, 207, 270) j1 j1 j1 b3 b3 b3 c2 c2 c2 g1 g1 g1 f2 f2 f2 h4 h4 h4 z3 z3 z3 z4 z4 z4 z5 z5 z5 13.4 au4 mode an example of the placement of tributaries assumed in au4 mode is illustrated in figure 13. for simplicity, this figure shows the frame on the od[7:0] bus when the stm-1 (sts-3) interface mode is enabled. in this case the outgoing vc4 is locked to an active offset of 522 with respect to the outgoing transport envelope frame. this particular example assumes a snapshot of the second frame of the tributary multiframe when the v2 bytes are present. this example illustrates a case where the vc4 carries tug3s, all tug3s carry tug2s, and all tug2s are configured to carry tu12s. figure 13 - sdh stm-1 carrying tu12 within tug3/au4 a1 a1 a1 a2 a2 a2 c1 c1 c1 - v2 v2 v2 spe b1 - - e1 - - f1 - - - spe spe spe spe d1 - - d2 - - d3 - - - spe spe spe spe h1 h1 h1 h2 h2 h2 h3 h3 h3 - spe spe spe spe b2 b2 b2 k1 - - k2 - - - spe spe spe spe d4 - - d5 - - d6 - - - spe spe spe spe d7 - - d8 - - d9 - - - spe spe spe spe d10 - - d11 - - d12 - - - spe spe spe spe z1 - - z2 - - e2 - - - spe spe spe spe row 1 2 3 4 5 6 7 8 9 col 1234567891011 192021 270 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 265 266 spe spe spe spe spe spe spe spe spe 267 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 268 269 first of 4 columns occupied by tu12 #1 of tug2 #1 of tug3 #1 of an stm-1 stream (column set is 19, 82, 145, 208) last of 4 columns occupied by tu12 #3 of tug2 #7 of tug3 #3 of an stm-1 stream (column set is 81, 144, 207, 270) j1 b3 c2 g1 f2 h4 z3 z4 z5
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 380 another example of the placement of tributaries assumed in au4 mode is illustrated in figure 14. for simplicity, this figure shows the frame on the od[7:0] bus when the stm-1 (sts-3) interface mode is enabled. in this case the outgoing vc4 is locked to an active offset of 522 with respect to the outgoing transport envelope frame. this example illustrates the case where the vc4 carries tug3s that are all configured to carry tu3s. figure 14 - sdh stm-1 carrying tu3 within tug3 a1 a1 a1 a2 a2 a2 c1 c1 c1 - h1 h1 h1 spe b1 - - e1 - - f1 - - - h2 h2 h2 spe d1 - - d2 - - d3 - - - h3 h3 h3 spe h1 h1 h1 h2 h2 h2 h3 h3 h3 - - - - spe b2 b2 b2 k1 - - k2 - - - - - - spe d4 - - d5 - - d6 - - - - - - spe d7 - - d8 - - d9 - - - - - - spe d10 - - d11 - - d12 - - - - - - spe z1 - - z2 - - e2 - - - - - - spe row 1 2 3 4 5 6 7 8 9 col 1234567891011 131415 270 poh poh poh poh poh poh poh poh poh poh poh poh poh poh poh poh poh poh 16 17 poh poh poh poh poh poh poh poh poh 18 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 268 269 first of 86 columns occupied by tu3 carried in tug3 #1 of an stm-1 stream last of 86 columns occupied by tu3 carried in tug3 #3 of an stm-1 stream j1 b3 c2 g1 f2 h4 z3 z4 z5 - - - - - - - - - 12 yet another example of the placement of tributaries assumed in au4 mode is illustrated in figure 15. for simplicity, this figure shows the frame on the od[7:0] bus when the stm-1 (sts-3) interface mode is enabled. in this case the outgoing vc4 is locked to an active offset of 522 with respect to the outgoing transport envelope frame. this particular example assumes a snapshot of the last frame of the tributary multiframe when the v4 bytes are present. this example illustrates a complex case where the vc4 carries tug3s and where tug3 #1 carries a tu3, tug3 #2 carries tug2s that are all configured to carry tu11s, and tug3 #3 carries tug2s that are all configured to carry tu12s.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 381 figure 15 - sdh stm-1 carrying mix of tu11, tu12, tu3 within tug3/au4 a1 a1 a1 a2 a2 a2 c1 c1 c1 - h1 h1 h1 spe b1 - - e1 - - f1 - - - h2 h2 h2 spe d1 - - d2 - - d3 - - - h3 h3 h3 spe h1 h1 h1 h2 h2 h2 h3 h3 h3 - - - - spe b2 b2 b2 k1 - - k2 - - - - - - spe d4 - - d5 - - d6 - - - - - - spe d7 - - d8 - - d9 - - - - - - spe d10 - - d11 - - d12 - - - - - - spe z1 - - z2 - - e2 - - - - - - spe row 1 2 3 4 5 6 7 8 9 col 1234567891011 131415 270 poh - poh - poh - poh - poh - poh - poh - poh - poh - 16 17 - - - - - - - - - 18 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 268 269 first of 86 columns occupied by tu3 carried in tug3 #1 of an stm-1 stream last of 4 columns occupied by tu12 #3 of tug2 #7 of tug3 #3 of an stm-1 stream (column set is 81, 144, 207, 270) j1 b3 c2 g1 f2 h4 z3 z4 z5 - - - - - - - - - 12 spe spe spe spe spe spe spe spe spe 19 v4 spe spe spe spe spe spe spe spe 20 v4 spe spe spe spe spe spe spe spe 21 first of 3 columns occupied by tu11 #1 of tug2 #1 of tug3 #2 of an stm-1 stream (column set is 20, 104, 188) in figure 15 above, the h1 to h3 byte in column 13 form the tu3 offset pointer. the h1 to h3 bytes in columns 14 and 15 are null pointer indications (npi) for tug3 #2 and #3. 13.5 bypass options the three tributary payload processors (vtpp) in each of the four stm-1 (sts-3) tributary processors (stp) in the tupp+622 may be individually disabled or bypassed using the corresponding tugen or tugbyp register bits, respectively. this enables the tupp+622 to support sts-1/au3/tug3 level bypass operation. incoming data destined to a disabled or bypassed processor is re- transmitted unchanged to the outgoing data after some delay. the amount of delay is fixed when the 19.44 mhz stm-1 interface mode for both the incoming and outgoing interfaces are selected. when either or both incoming and outgoing interfaces are set to the 77.76 mhz stm-4 interface mode, the amount of delay is also dependent on the relative phase of the corresponding incoming frame pulse (ic1j1) and the gsclk frame pulse (gsclk_fp). figure 26 and figure 27 show the functional timing of possible bypass delays for the stm-1 (sts-3) and the stm-4 (sts-12) interface modes, respectively. for stm-1 (au4) bypass operation, all three tributary payload processors (vtpp) of the corresponding stm-1 (sts-3) tributary processor (stp) must be bypassed by setting the tugen and tugbyp bits high. tributary performance monitoring of the stm-1 (au4) stream remains active in this bypass configuration.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 382 for stm-4-4c bypass, all three tributary payload processors (vtpp) in each of the four stm-1 (sts-3) tributary processors (stp) must be disabled by setting the tugen bits low. tributary performance monitoring of the stm-4-4c stream is not required and is disabled in this bypass configuration. 13.6 power sequencing due to esd protection structures in the pads, it is necessary to exercise caution when powering a device up or down. esd protection devices behave as diodes between power supply pins and from i/o pins to power supply pins. under extreme conditions, it is possible to damage these esd protection devices or trigger latch-up. the recommended power supply sequencing is as follows: 1. to prevent damage to the esd protection on the device inputs, the maximum dc input current specification must be respected. this is accomplished by either ensuring that the vdd/vddi power is applied before input pins are driven or by increasing the source impedance of the driver so that the maximum driver short circuit current is less than the maximum dc input current specification (20 ma). 2. power supply to the core (vddi) must be applied after vdd have been applied or they must be current limited to the maximum latch-up current specification (100 ma). 3. power down the device in the reverse sequence. use the above current limiting technique for the vddi power supply. small offsets in vdd and vddi discharge times will not damage the device. 13.7 jtag support the tupp+622 supports the ieee boundary scan specification as described in the ieee 1149.1 standards. the test access port (tap) consists of the five standard pins, trstb, tck, tms, tdi and tdo, used to control the tap controller and the boundary scan registers. the trstb input is the active low reset signal used to reset the tap controller. tck is the test clock used to sample data on input, tdi and to output data on output, tdo. the tms input is used to direct the tap controller through its states. the basic boundary scan architecture is shown below.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 383 figure 16 - boundary scan architecture boundary scan register control tdi tdo device identification register bypass register instruction register and decode trstb tms tck test access port controller mux dff select tri-state enable the boundary scan architecture consists of a tap controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. the tap controller interprets the tms input and generates control signals to load the instruction and data registers. the instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. the bypass register offers a single bit delay from primary input, tdi to primary output, tdo. the device identification register contains the device identification code.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 384 the boundary scan register allows testing of board inter-connectivity. the boundary scan register consists of a shift register place in series with device inputs and outputs. using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, tdo. in addition, patterns can be shifted in on primary input, tdi and forced onto all digital outputs. 13.7.1 tap controller the tap controller is a synchronous finite state machine clocked by the rising edge of primary input, tck. all state transitions are controlled using primary input, tms. the finite state machine is described below.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 385 figure 17 - tap controller finite state machine test-logic-reset run-test-idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir trstb=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 all transitions dependent on input tms 0 0 0 0 0 1
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 386 test-logic-reset: the test logic reset state is used to disable the tap logic when the device is in normal mode operation. the state is entered asynchronously by asserting input, trstb. the state is entered synchronously regardless of the current tap controller state by forcing input, tms high for 5 tck clock cycles. while in this state, the instruction register is set to the idcode instruction. run-test-idle: the run test/idle state is used to execute tests. capture-dr: the capture data register state is used to load parallel data into the test data registers selected by the current instruction. if the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. loading occurs on the rising edge of tck. shift-dr: the shift data register state is used to shift the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-dr: the update data register state is used to load a test register's parallel output latch. in general, the output latches are used to control the device. for example, for the extest instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. the parallel output latches are updated on the falling edge of tck. capture-ir: the capture instruction register state is used to load the instruction register with a fixed instruction. the load occurs on the rising edge of tck.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 387 shift-ir: the shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-ir: the update instruction register state is used to load a new instruction into the instruction register. the new instruction must be scanned in using the shift-ir state. the load occurs on the falling edge of tck. the pause-dr and pause-ir states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. the tdo output is enabled during states shift-dr and shift-ir. otherwise, it is tri-stated. 13.7.2 boundary scan instructions the following is a description of the standard instructions. each instruction selects an serial test data register path between input, tdi, and output, tdo. bypass the bypass instruction shifts data from input tdi to output tdo with one tck clock period delay. the instruction is used to bypass the device. extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is place between input tdi and output tdo. primary device inputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. primary device outputs can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 388 sample the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan register is placed between tdi and tdo. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. idcode the identification instruction is used to connect the identification register between tdi and tdo. the device's identification code can then be shifted out using the shift-dr state. stctest the single transport chain instruction is used to test out the tap controller and the boundary scan register during production test. when this instruction is the current instruction, the boundary scan register is connected between tdi and tdo. during the capture-dr state, the device identification code is loaded into the boundary scan register. the code can then be shifted out on output tdo using the shift-dr state.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 389 14 functional timing the timing of the tupp+622 stm-1 input signals is illustrated in figure 18 where n is {1, 2, 3, 4}. this diagram shows a simple sts-3 case that outlines the function of the various input signals associated with each of the four input buses when the tupp+622 is in stm-1 (sts-3) input interface mode (ihsmodeb set high). data on id[7:0] (id[15:8], id[23:16], id[31:24]) is sampled on the rising edge of sclk. the bytes forming the three sts-1 synchronous payload envelopes are identified by the ipl[1] (ipl[2], ipl[3], ipl[4]) signal being set high. the ic1j1[1] (ic1j1[2], ic1j1[3], ic1j1[4]) signal pulses high while ipl[1] (ipl[2], ipl[3], ipl[4]) is low to mark the position of the first c1 byte in the sts-3 transport envelope. the ic1j1[1] (ic1j1[2], ic1j1[3], ic1j1[4]) signal is set high for three sclk periods while ipl[1] (ipl[2], ipl[3], ipl[4]) is also set high to mark the j1 bytes of each sts-1 spe. the itmf[1] (itmf[2], itmf[3], itmf[4]) signal is selectable to mark the third byte after j1 of the first tributary in an sts-1 spe or the h4 byte in the last (fourth) frame of a tributary multiframe. in this diagram, itmf[1] (itmf[2], itmf[3], itmf[4]) is shown to be marking the last h4 byte of the tributary multiframe in sts-1 #1 and sts-1 #3. the h4 byte in sts-1 #2, as shown, is not last in the tributary multiframe. in this simple example, all sts-1 spes are aligned to the sts-3 transport envelope such that the j1 bytes directly follow the c1 bytes and no sts-1 pointer justification events are occurring. other alignments are possible. the four input buses can be independently configured to handle sts-1/au3 or au4 and the spe/vc alignments of the input buses may be different. however, the transport frame alignments of the four input buses must be identical. that is, the c1 portion of all the ic1j1[4:1] signals must be coincident. this diagram also applies to the au3 mode as it is equivalent to the sts-1 mode, except for nomenclature.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 390 figure 18 - stm-1 input bus timing - simple sts-1/au3 case ic1j1[n] sclk ipl[n] id[7:0] (n=1) id[15:8] (n=2) id[23:16] (n=3) id[31:24] (n=4) a1 a1 a2 a2 a2 c1 c1 c1 a1 h2 h3 h3 h3 sts-1 #1 spe j1 byte sts-1 #2 spe j1 byte sts-1 #3 spe j1 byte no stuffing occuring h4 h4 h4 j1 j1 j1 itmf[n] (itmfh4=1) figure 19 shows a more complex sts-3 case that illustrates the flexibility provided by the various input signals associated with each of the four input buses when the tupp+622 is in stm-1 (sts-3) input interface mode (ihsmodeb set high) (n is {1, 2, 3, 4}). data on id[7:0] (id[15:8], id[23:16], id[31:24]) is sampled on the rising edge of sclk. the bytes forming the three sts-1 synchronous payload envelopes are identified by the ipl[1] (ipl[2], ipl[3], ipl[4]) signal being set high. this example shows a negative stuff event occurring on sts-1 #2 and a positive stuff event occurring on sts-1 #3. the ic1j1[1] (ic1j1[2], ic1j1[3], ic1j1[4]) signal pulses high while ipl[1] (ipl[2], ipl[3], ipl[4]) is low to mark the position of the c1 byte of sts-1 #1. the ic1j1[1] (ic1j1[2], ic1j1[3], ic1j1[4]) signal pulses high again to mark the j1 byte of each of the three sts-1 spes. the itmf[1] (itmf[2], itmf[3], itmf[4]) signal is selectable to mark the third byte after j1 in an sts-1 spe or the h4 byte in the last (fourth) frame of a tributary multiframe. in this diagram, itmf[1] (itmf[2], itmf[3], itmf[4]) is shown to be marking the v1 byte of the first tributary multiframe in sts-1 #2. the three sts-1 spes are shown to have different alignments to the sts-3 transport envelope and the alignment is changing for two of the sts-1 spes (sts-1 #1 and #2) due to the pointer justification events shown. other alignments are possible. the four input buses can be independently configured to handle sts- 1/au3 or au4 and the spe/vc alignments of the input buses may be different. however, the transport frame alignments of the four input buses must be identical. that is, the c1 portion of all the ic1j1[4:1] signals must be coincident.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 391 this diagram also applies to the au3 mode as it is equivalent to sts-1 mode, except for nomenclature. figure 19 - stm-1 input bus timing - complex sts-1 / au3 case sclk a1 a1 a2 a2 a2 c1 c1 c1 a1 h1 h1 h2 h2 h2 h3 h3 h1 negative stuff byte for sts-1 #2 spe which happens to carry the j1 byte positive stuff for sts-1 #3 spe sts-1 #1 spe j1 byte j1 j1 v1 v1 byte of first tributary in sts-1 #2 v1 v1 byte of second tributary in sts-1 #2 ic1j1[n] ipl[n] id[7:0] (n=1) id[15:8] (n=2) id[23:16] (n=3) id[31:24] (n=4) itmf[n] (itmfh4=0) the timing of the tupp+622 input buses when it is in stm-1 (sts-3) input interface mode (ihsmodeb set high) is illustrated in figure 20 where n is {1, 2, 3, 4}. this diagram shows the relationships of the input signals in sts-1 mode associated with each of the four input buses. data on id[7:0] (id[15:8], id[23:16], id[31:24]) is sampled on the rising edge of sclk. the ic1j1[1] (ic1j1[2], ic1j1[3], ic1j1[4]) signal pulses high when ipl[1] is set low to mark the position of the c1 byte of the first sts-1 stream in every frame of the sts-3 transport envelope. ic1j1[1] (ic1j1[2], ic1j1[3], ic1j1[4]) pulses high when ipl[1] (ipl[2], ipl[3], ipl[4]) is set high to mark the j1 byte in each sts-1 stream. ipl[1] (ipl[2], ipl[3], ipl[4]) identifies the spe bytes on id[7:0] (id[15:8], id[23:16], id[31:24]). the itmf[1] (itmf[2], itmf[3], itmf[4]) input marks the frame containing v1 bytes. it is sampled only at the first v1 byte position of the first sts-1 stream. the bytes forming the various tributary synchronous payload envelopes are identified by the itpl[1] (itpl[2], itpl[3], itpl[4]) signal being set high when the vt/tu pointer interpretation is disabled. the itv5[1] (itv5[2], itv5[3], itv5[4]) signal pulses high to mark the v5 bytes of each incoming tributary when the vt/tu pointer interpretation is disabled. in this example, all sts-1 spes are aligned to the sts-3 transport envelope such that the j1 bytes
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 392 directly follow the c1 bytes. other alignments are possible. the four input buses can be independently configured to handle sts-1/au3 or au4 and the spe/vc alignments of the input buses may be different. however, the transport frame alignments of the four input buses must be identical. that is, the c1 portion of all the ic1j1[4:1] signals must be coincident. this diagram also applies to the au3 mode as it is equivalent to sts-1 mode, except for nomenclature. figure 20 - stm-1 input bus timing - sts-1 / au3 (vt/tu pointer interpretation disabled) sclk itpl[n] itv5[n] itm f [n ] ic1j1[n] ip l [n] implicit location of sts-1 spe j1 bytes a2 c1 c1 c1 h1 h1 h2 h2 h2 h3 h3 h1 h3 no stuff event v1 byte vt #1, sts-1 #1 v5 byte vt #1, sts-1 #2 j1 j1 j1 v1 v1 v1 v1 v1 v1 v1 v1 byte vt #1, sts-1 #2 v1 byte vt #1, sts-1 #3 v5 v1 bytes vt #2 j2 j2 byte vt #1, sts-1 #1 id[7:0] (n=1) id[15:8] (n=2) id[23:16] (n=3) id[31:24] (n=4) (itmfh4=0) figure 21 shows timing relationships of the various input signals in the au4 mode associated with each of the four input buses when the tupp+622 is in stm-1 (sts-3) input interface mode (ihsmodeb set high) (n is {1, 2, 3, 4}). data on id[7:0] (id[15:8], id[23:16], id[31:24]) is sampled on the rising edge of sclk. the bytes forming the au4 virtual container are identified by the ipl[1] (ipl[2], ipl[3], ipl[4]) signal being set high. this example shows a negative stuff occurring for the vc4. the ic1j1[1] (ic1j1[2], ic1j1[3], ic1j1[4]) signal pulses high while ipl[1] (ipl[2], ipl[3], ipl[4]) is set low to mark the position of the single c1 byte in the stm-1 transport envelope. the itmf[1] (itmf[2], itmf[3], itmf[4]) signal is selectable to mark the third byte after j1, or the h4 byte in the last (fourth) frame of a tributary multiframe. in this diagram, itmf[1] (itmf[2], itmf[3], itmf[4]) is shown to be marking the final h4 byte of the tributary
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 393 multiframe. the ic1j1[1] (ic1j1[2], ic1j1[3], ic1j1[4]) signal pulses high to mark the single j1 byte of the vc4. this diagram applies to input buses in au4 mode, regardless of whether individual tributary payload processors are configured for tug3 or tu3 mode. the four input buses can be independently configured to handle sts-1/au3 or au4 and the spe/vc alignments of the input buses may be different. however, the transport frame alignments of the four input buses must be identical. that is, the c1 portion of all the ic1j1[4:1] signals must be coincident. figure 21 - stm-1 input bus timing - au4 case sclk a1 a1 a2 a2 a2 c1 a1 h1 h1 h2 h2 h2 h1 negative stuff for vc4 which happens to carry the j1 byte h4 xx ic1j1[n] ipl[n] id[7:0] (n=1) id[15:8] (n=2) id[23:16] (n=3) id[31:24] (n=4) itmf[n] (itmfh4=1)
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 394 figure 22 shows a simple four sts-3 case that outlines the function of the various input signals associated with the id[7:0] input bus when the tupp+622 is in stm-4 (sts-12) input interface mode (ihsmodeb set low). data on id[7:0] is sampled on the rising edge of hsclk. the bytes forming the sts-1 synchronous payload envelopes are identified by the ipl[1] signal being set high. the ic1j1[1] signal pulses high while ipl[1] is low to mark the position of the first c1 byte in the sts-12 transport envelope. the ic1j1[1] signal is set high for one hsclk periods while ipl[1] is also set high to mark the j1 byte of each sts-1 spe. in this diagram, ic1j1[1] is shown to be marking the j1 byte of sts-3 #1 sts-1 #1. the itmf[1] signal is selectable to mark the third byte after j1 of the first tributary in an sts-1 spe or the h4 byte in the last (fourth) frame of a tributary multiframe. in this diagram, itmf[1] is shown to be marking the v1 byte of the first tributary multiframe in sts-3 #1 sts-1 #1. this diagram also applies to the au3 mode as it is equivalent to the sts-1 mode, except for nomenclature. figure 22 - stm-4 input bus timing - sts-1/au3 case itmf[1] hsclk id[7:0] toh #1 c1 toh #2 c1 toh #3 c1 spe #1 byt 1 spe #2 byt 1 spe #3 byt 1 spe #2 byt 262 spe #2 byt 263 spe #3 byt 263 ipl[1] pje ic1j1[1] idp[1] spe #1 byt 263 spe #3 byt 262 spe #1 byt 262 sts-3 #1 sts-3 #4 sts-3 #3 sts-3 #2 sts-3 #1 sts-1 #1 poh j1 sts-3 #3 sts-1 #2 pso sts-3 #1 sts-1 #1 v1 sts-1 #1's sts-1 #3's sts-1 #2's (itmfh4=0)
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 395 the timing of the tupp+622 output buses when it is in stm-1 (sts-3) output interface mode (ohsmodeb set high) is illustrated in figure 23 where n is {1, 2, 3, 4}. this diagram shows the relationships of the output signals in sts-1 mode associated with each of the four output buses. data on od[7:0] (od[15:8], od[23:16], od[31:24]) is updated on the rising edge of sclk. the oc1j1v1[1] (oc1j1v1[2], oc1j1v1[3], oc1j1v1[4]) signal pulses high with opl[1] (opl[2], opl[3], opl[4]) signal set low to mark the position of the c1 byte of the first sts-1 stream in every frame of the sts-3 transport envelope on od[7:0] (od[15:8], od[23:16], od[31:24]). in sts-1 mode, the position of the j1 bytes and the sts-1 spes is determined by the value written to the stp outgoing pointer msb and lsb registers. all three sts-1 spes are aligned in the sts-3 transport envelope. this register settable alignment is reflected in the outgoing stream control signals oc1j1v1[1] (oc1j1v1[2], oc1j1v1[3], oc1j1v1[4]) and opl[1] (opl[2], opl[3], opl[4]). oc1j1v1[1] (oc1j1v1[2], oc1j1v1[3], oc1j1v1[4]) pulses high with opl[1] (opl[2], opl[3], opl[4]) signal set high to mark all three j1 bytes and the third byte after j1 of the first tributary in each sts-1 stream. opl[1] (opl[2], opl[3], opl[4]) identifies the spe bytes on od[7:0] (od[15:8], od[23:16], od[31:24]). the otmf[1] (otmf[2], otmf[3], otmf[4]) input marks the frame containing v1 bytes in od[7:0] (od[15:8], od[23:16], od[31:24]). it is sampled only at the first v1 byte position of the first sts-1 stream. the bytes forming the various tributary synchronous payload envelopes are identified by the otpl[1] (otpl[2], otpl[3], otpl[4]) signal being set high. the otv5[1] (otv5[2], otv5[3], otv5[4]) signal pulses high to mark the v5 bytes of each outgoing tributary. the tpoh[1] (tpoh[2], tpoh[3], tpoh[4]) signal marks the tributary path overhead bytes (v5, j2, z6 and z7) of each outgoing tributary. in this simple example, all sts-1 spes are aligned to the sts-3 transport envelope such that the j1 bytes directly follow the c1 bytes. other alignments are possible. the four output buses can be independently configured to handle sts-1/au3 or au4 and the spe/vc alignments of the output buses may be different. this diagram also applies to the au3 mode as it is equivalent to sts-1 mode, except for nomenclature.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 396 figure 23 - stm-1 output bus timing - sts-1 spes / au3 vcs case sclk otpl[n] otv5[n] otmf[n] (otmfh4=0) oc1j1v1[n] opl[n] tpoh[n] implicit location of sts-1 spe j1 bytes a2 c1 c1 c1 h1 h1 h2 h2 h2 h3 h3 h1 h3 no stuff events possible v1 byte vt #1, sts-1 #1 v5 byte vt #1, sts-1 #2 j1 j1 j1 v1 v1 v1 v1 v1 v1 v1 v1 byte vt #1, sts-1 #2 v1 byte vt #1, sts-1 #3 v5 v1 bytes vt #2 j2 j2 byte vt #1, sts-1 #1 od[7:0] (n=1) od[15:8] (n=2) od[23:16] (n=3) od[31:24] (n=4)
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 397 the timing of the tupp+622 output buses when it is in stm-1 (sts-3) output interface mode (ohsmodeb set high) is illustrated in figure 24 where n is {1, 2, 3, 4}. this diagram shows the relationships of the output signals in au4 mode associated with each of the four output buses. the operation of the various signals is analogous to the sts-1 mode, except that there is only a single j1. this timing applies regardless of whether individual tributary payload processors are configured for tug3 or tu3 mode. data on od[7:0] (od[15:8], od[23:16], od[31:24]) is updated on the rising edge of sclk. the oc1j1v1[1] (oc1j1v1[2], oc1j1v1[3], oc1j1v1[4]) signal pulses high with opl[1] (opl[2], opl[3], opl[4]) signal set low to mark the position of the single c1 byte in every frame of the au4 transport envelope on od[7:0] (od[15:8], od[23:16], od[31:24]). in au4 mode, the position of the single j1 byte and the vc4 is determined by the value written to the stp outgoing pointer msb and lsb registers. this register settable alignment is reflected in the outgoing stream control signals oc1j1v1[1] (oc1j1v1[2], oc1j1v1[3], oc1j1v1[4]) and opl[1] (opl[2], opl[3], opl[4]). oc1j1v1[1] (oc1j1v1[2], oc1j1v1[3], oc1j1v1[4]) pulses high with opl[1] (opl[2], opl[3], opl[4]) signal set high to mark the j1 byte and the third byte after j1 of the first tributary in the au4 stream. opl[1] (opl[2], opl[3], opl[4]) identifies the payload bytes on od[7:0] (od[15:8], od[23:16], od[31:24]). the otmf[1] (otmf[2], otmf[3], otmf[4]) input marks the frame containing v1 bytes in od[7:0] (od[15:8], od[23:16], od[31:24]). it is sampled only at the j1 plus one byte position of the first tug3 stream. the bytes forming the various tributary synchronous payload envelopes are identified by the otpl[1] (otpl[2], otpl[3], otpl[4]) signal being set high. the otv5[1] (otv5[2], otv5[3], otv5[4]) signal pulses high to mark the v5 bytes of each outgoing tributary. the tpoh[1] (tpoh[2], tpoh[3], tpoh[4]) signal pulses high to mark the tributary path overhead bytes (v5, j2, z6 and z7) of each outgoing tributary. in this simple example, the vc4 is aligned to the stm-1 transport envelope such that the j1 byte directly follows the c1 byte. other alignments are possible the four output buses can be independently configured to handle sts- 1/au3 or au4 and the spe/vc alignments of the output buses may be different.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 398 figure 24 - stm-1 output bus timing - au4 vc case od[7:0] (n=1) od[15:8] (n=2) od[23:16] (n=3) od[31:24] (n=4) sclk (otmfh4=0) opl[n] oc1j1v1[n] im plicit loca tion of vc4 j1 byte a2 c1 x x h4 j1 national bytes first r column of tug3 #1 v5 v1 v1 byte tu #1, tug2 #1, tug3 #1 last h4 b yte in tributary multiframe v5 byte tu #1, tug2 #1, tug3 #1 fixed stuff columns rrrrrr rrrrrr z6 z6 byte tu #1, tug2 #1, tug3 #3 otv5[n] otpl[n] tpoh[n] otmf[n] figure 25 shows a simple four sts-3 case that outlines the function of the various output signals associated with the od[7:0] output bus when the tupp+622 is in stm-4 (sts-12) output interface mode (ohsmodeb set low). data on od[7:0] is updated on the rising edge of hsclk. the oc1j1v1[1] signal pulses high with opl[1] signal set low to mark the position of the c1 byte of the first sts-1 stream in every frame of the sts-12 transport envelope on od[7:0]. in sts-1 mode, the position of the j1 bytes and the sts-1 spes in an sts-3 is determined by the value written to the corresponding stp outgoing pointer msb and lsb registers. all three sts-1 spes are aligned in an sts-3 stream. this register settable alignment is reflected in the outgoing control signals oc1j1v1[1] and opl[1]. oc1j1v1[1] pulses high with opl[1] set high to mark the j1 bytes and the third byte after j1 of the first tributary in each sts-1 stream within the sts-12. opl[1] identifies the spe bytes on od[7:0]. the otmf[1] input marks the frame containing v1 bytes. it is sampled only at the first v1 byte position of the first sts-1 stream in each of the sts-3 #1, #2, #3 and #4
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 399 streams within the sts-12 transport envelope. the bytes forming the various tributary synchronous payload envelopes are identified by the otpl[1] signal being set high. the otv5[1] signal pulses high to mark the v5 bytes of each outgoing tributary. the tpoh[1] signal marks the tributary path overhead bytes (v5, j2, z6 and z7) of each outgoing tributary. this diagram also applies to the au3 mode as it is equivalent to sts-1 mode, except for nomenclature. the four sts-3?s (stm-1?s) in the outgoing sts-12 stream can be independently configured to handle sts-1/au3 or au4 and the spe/vc alignments of the sts- 3 (stm-1) streams may be different. figure 25 - stm-4 output bus timing - sts-1 spes / au3 vcs case otmf[1] od[7:0] toh #1 c1 toh #2 c1 toh #3 c1 spe #1 byt 1 spe #2 byt 1 spe #3 byt 1 spe #2 byt 262 spe #2 byt 263 spe #3 byt 263 otpl[1] spe #1 byt 263 spe #3 byt 262 spe #1 byt 262 sts-3 #1 sts-3 #4 sts-3 #3 sts-3 #2 sts-3 #1 sts-1 #1 poh j1 sts-3 #1 sts-1 #1 vt ptr. v1 sts-1 #1's sts-1 #3's sts-1 #2's sts-3 #3 sts-1 #3 vtoh v5 sts-3 #1 sts-1 #2 j1 sts-3 #1 sts-1 #3 j1 sts-3 #1 sts-1 #2 v1 sts-3 #1 sts-1 #3 v1 hsclk otv5[1] (otmfh4=0) opl[1] oc1j1v1[1] tpoh[1]
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 400 the three tributary payload processors (vtpp) in an stm-1 (sts-3) tributary processor (stp) may be individually disabled or bypassed using the corresponding tugen or tugbyp register bits, respectively. incoming data destined to a disabled or bypassed processor is re-transmitted unchanged to the outgoing data after some delay. the amount of delay from the incoming to the outgoing data stream is a function of the internal data-path pipeline delay. figure 26 shows the delay for the end to end data path delay from id[7:0] input to od[7:0] output in the stm-1 (sts-3) interface mode (ihsmodeb and ohsmodeb set high). the delay from the rising edge of sclk where tupp+622 samples id[7:0] to the rising edge of sclk where a downstream device samples od[7:0] is 7 cycles. this diagram also applies to the id[15:8], id[23:16] and id[31:24] input buses and their corresponding output buses. this end-to-end data-path delay is also applicable to the transport frame delay between ic1j1[1] (ic1j1[2], ic1j1[3], ic1j1[4]) and the oc1 portion of oc1j1v1[1] (oc1j1v1[2], oc1j1v1[3], oc1j1v1[4]) in normal tributary processing mode. figure 26 - stm-1 (sts-3) interface, by-passed and normal transport frame delay functional timing sclk oc1j1v1[1] a1 c1 a1 a1 a2 a2 a2 c1 c1 c1 c1 c1 a2 od[7:0] id[7:0] ic1j1[1] c1 c1
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 401 the three tributary payload processors (vtpp) in each of the four stm-1 (sts-3) tributary processors (stp) in the tupp+622 may be individually disabled or bypassed using the corresponding tugen or tugbyp register bits, respectively. incoming data destined to a disabled or bypassed processor is re-transmitted unchanged to the outgoing data after some delay. the amount of delay from the incoming to the outgoing data stream is a function of the internal data-path pipeline delay and the relative phase of the corresponding incoming frame pulse (ic1j1[1]) and the gsclk_fp input signal. figure 27 shows the end to end data path delay from id[7:0] input to od[7:0] output for the four possible alignments of ic1j1[1] in relation to gsclk_fp when tupp+622 is in the stm-4 (sts-12) interface mode (ihsmodeb and ohsmodeb set low). the delay from the rising edge of hsclk where tupp+622 samples id[7:0] to the rising edge of hsclk where a downstream device samples od[7:0] is 30, 31, 32 or 33 cycles for an ic1/gsclk_fp offset of zero, one, two or three respectively. this end-to-end data-path delay is also applicable to the transport frame delay between ic1j1[1] and the oc1 portion of oc1j1v1[1] in normal tributary processing mode. figure 27 - stm-4 (sts-12) interface, by-passed and normal transport frame delay functional timing hsclk ic1j1[1] c1 oc1j1v1[1] c1 c1 c1 a2 od[7:0] id[7:0] a2 c1 a2 a2 a2 a2 a2 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 a2 a2 gsclk_fp 0123 ic1/gsclk_fp offset by 3 clk.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 402 the tributary overhead serial interface associated with the stm-1 (sts-3) tributary processor (stp) #1 is shown in figure 28. the tributary path overhead bytes in each of the sts-1 (au3) or tug3 streams on id[7:0] are individually serialized on poh[3:1]. the most significant bit of the v5 byte of the first tributary (tu#1, tug2 #1) of each sts-1 stream is identified by a logic high value on the corresponding pohen[3:1] output. all four tributary path overhead bytes (v5, j2, z6, z7) are shifted out once per payload frame. since the nominal arrival rate of overhead is once per multiframe, each overhead byte is presented on poh an average of four times. to distinguish the first presentation of an overhead byte from subsequent repeat presentations, the corresponding pohen[3:1] output is set high to mark a fresh byte and set low to mark a stale byte. pohck provides timing for the poh[3:1], pohfp[3:1] and pohen[3:1] outputs. pohck is a 9.72 mhz clock and run continuously. tributaries on poh are arranged in the order of transmission as in the incoming data stream id[7:0]. i.e., tu #1 of tug2 #1, tu#1 of tug2 #2, ... tu #1 of tug2 #7, tu #2 of tug2 #1, ... tu #2 of tug2 #7, tu #3 of tug2 #1, ... tu #4 of tug2 #7. timeslot assignment on poh is unrelated to the configuration of the tributary group. timeslots for four tributaries are always reserved for any tributary group even if it is configured for tu12, vt3 or tu2. at timeslots devoted to non- existent tributaries, for example, tributary 2, 3 and 4 of a tug2 configured for tu2, poh and pohen will be set low. the path overhead frame pulse, pohfp, identifies the most significant bit of the first tributary (tu #1 of tug2 #1) on poh. in tu3 mode, the poh stream carries the nine path overhead bytes. the bytes are shifted out twice per payload frame. the assignment of tu3 poh bytes to lower order tributary overhead timeslots are: tu3, j1 -> tu #1, tug2 #1, v5 and tu #3, tug2 #1, v5 tu3, b3 -> tu #1, tug2 #1, j2 and tu #3, tug2 #1, j2 tu3, c2 -> tu #1, tug2 #1, z6 and tu #3, tug2 #1, z6 tu3, g1 -> tu #1, tug2 #1, z7 and tu #3, tug2 #1, z7 tu3, f2 -> tu #1, tug2 #2, v5 and tu #3, tug2 #2, v5 tu3, h4 -> tu #1, tug2 #2, j2 and tu #3, tug2 #2, j2 tu3, z3 -> tu #1, tug2 #2, z6 and tu #3, tug2 #2, z6
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 403 tu3, z4 -> tu #1, tug2 #2, z7 and tu #3, tug2 #2, z7 tu3, z5 -> tu #1, tug2 #3, v5 and tu #1, tug2 #3, v5 this functional timing also applies to tributary overhead serial interfaces, poh[6:4], poh[9:7] and poh[12:10] associated with the stm-1 (sts-3) tributary processor (stp) #2, #3 and #4, respectively.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 404 figure 28 - tributary path overhead serialization functional timing p o h c k p o h e n [ 3 : 1 ] p o h f p [ 3 : 1 ] p o h [ 3 : 1 ] b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 1 b 2 b 3 x t u # 1 , t u g 2 # 1 , v 5 b y t e t u # 1 , t u g 2 # 1 , j 2 b y t e t u # 1 , t u g 2 # 1 , z 6 b y t e t u # 1 , t u g 2 # 1 , z 7 b y t e p o h c k v 5 j 2 z 6 z 7 v 5 j 2 z 6 z 7 v 5 t u # 1 , t u g 2 # 1 t u # 1 , t u g 2 # 2 t u # 1 , t u g 2 # 3 j 2 z 6 z 7 v 5 j 2 z 6 z 7 t u # 4 , t u g 2 # 7 x x p o h f p [ 3 : 1 ]
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 405 figure 28 shows the timing of the receive alarm port associated with the stm-1 (sts-3) tributary processor (stp) #1. timing is provided by the pohck output which is a continuous 9.72 mhz clock. the bip-2, rdi, auxiliary rdi, pdi and lom indications of all the tributaries in the incoming stream are combined and reported on the rad[1] output. the bits labeled b1 and b2 reports the number of bip-2 errors. if the number of bip-2 errors is one, only one of b1 is set high. both b1 and b2 are set high when two bip-2 errors are detected. the bit labeled r and ar reports the remote defect indication (rdi) and auxiliary remote defect indication (ardi) status of the associated tributary. they are set high due to incoming ais, lop, pslm, pslu, tim, tiu and lom. the bit labeled p report the path defect indication (pdi-p) due to tributary path defect indication pdi-v, ais, lop and uneq states. the pdi-p indications allow a downstream device where the tributaries are aggregated into an spe to form a c2 byte containing the count of tributaries in alarm state. the bit labeled l reports the loss of multiframe state. tributaries timeslots on rad[1] are arranged in the order of transmission as in the incoming data stream id[7:0]. i.e., tu #1 of tug2 #1 tug3 #1, tu #1 of tug2 #1 tug3 #2, tu #1 of tug2 #1 tug3 #3, tu#1 of tug2 #2 tug3 #2, ... tu #1 of tug2 #7 tug3 #3, tu #2 of tug2 #1 tug3 #1, ..., tu #2 of tug2 #7 tug3 #3, ..., tu #4 of tug2 #7 tug3 #3. timeslot assignment on rad[1] is unrelated to the configuration of the tributary group. timeslots for four tributaries are always reserved for any tributary group even if it is configured for tu12, vt3 or tu2. at timeslots devoted to non-existent tributaries, for example, tributary 2, 3 and 4 of a tug2 configured for tu2, rad[1] will be set low. the path overhead frame pulse, pohfp[1], identifies the bip-2 error indication for the odd-numbered bits of the first tributary (tu #1 of tug2 #1 sts-1 #1) on rad[1]. when a tug3 stream is configured in tu3 mode, the segregation of rad[1], for that tug3, into tributary timeslots are dissolved. any bit normally carrying tributary bip-2 indications may carry a tu3 bip-8 error indication. all remaining bits will report the associated state of the tu3 stream simultaneously. this functional timing also applies to receive alarm ports, rad[2], rad[3] and rad[4] associated with the stm-1 (sts-3) tributary processor (stp) #2, #3 and #4, respectively. the path overhead frame pulse signals, pohfp[4], pohfp[7] and pohfp[10], identify the bip-2 error indication for the odd-numbered bits of the first tributary (tu #1 of tug2 #1 sts-1 #1) on rad[2], rad[3] and rad[4] respectively. when a tug3 is bypassed by setting corresponding tugen bit in the vtpp configuration register low, no performance monitoring is performed on
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 406 that tug3 stream. consequently, the timeslots associated with the bypassed stream on the rad stream are invalid.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 407 figure 29 - receive alarm port functional timing p o h c k p o h f p [ 1 ] r a d [ 1 ] p o h c k t u g 3 # 1 t u g 3 # 2 t u g 3 # 3 t u # 1 , t u g 2 # 1 t u # 1 , t u g 2 # 2 t u # 1 , t u g 2 # 3 t u # 4 , t u g 2 # 7 x x p o h f p [ 1 ] t u g 3 # 1 t u g 3 # 2 t u g 3 # 3 t u g 3 # 1 t u g 3 # 2 t u g 3 # 3 t u g 3 # 1 t u g 3 # 2 t u g 3 # 1 t u g 3 # 2 t u g 3 # 3 t u g 3 # 2 t u g 3 # 3 t u # 1 , t u g 2 # 4 t u # 4 , t u g 2 # 6 t u # 1 , t u g 2 # 1 , t u g 3 # 1 t u # 1 , t u g 2 # 1 , t u g 3 # 2 t u # 1 , t u g 2 # 1 , t u g 3 # 3 t u # 1 , t u g 2 # 2 , t u g 3 # 1 t u # 1 , t u g 2 # 2 , t u g 3 # 2 b 1 b 2 r b 1 b 2 r p l a r b 1 b 2 r p l a r b 1 b 2 r p l a r b 1 b 2 r p l a r
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 408 15 absolute maximum ratings maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. they are not indicative of normal operating conditions. table 7 -tupp+622 absolute maximum ratings ambient temperature under bias -40c to +85c storage temperature -40c to +125c supply voltage (+3.3 volt v dd3.3 ) -0.3v to +4.6v supply voltage (+2.5 volt v dd2.5 ) -0.3v to +3.5v voltage on any pin -0.3v to +6.0v static discharge voltage 1000 v latch-up current 100 ma dc input current 20 ma lead temperature +230c absolute maximum junction temperature +150c
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 409 16 d.c. characteristics (t a = -40c to +85c, v dd3.3 = 3.3 v 0.3 v, v dd2.5 = 2.5 v 0.2 v) table 8 -tupp+622 d.c. characteristics symbol parameter min typ max units conditions v dd3.3 3.3v power supply 3.0 3.3 3.6 volts note 5. v dd2.5 2.5v power supply 2.3 2.5 2.7 volts note 5. v il input low voltage -0.5 0.8 volts guaranteed input low voltage. v ih input high voltage 2.0 5.5 volts guaranteed input high voltage. note 6. v ol output or bi- directional low voltage 0.4 volts i ol = -8 ma for all outputs. notes 3, 5. v oh output or bi- directional high voltage 2.4 volts i oh = 8 ma for all outputs. notes 3, 5. v t+ schmitt triggered input high voltage 2.0 5.5 volts v t- schmitt triggered input low voltage -0.5 0.8 volts v th schmitt triggered input hysteresis voltage 0.5 volts note 6. i ilpu input low current +10 45 +100 a v il = gnd, notes 1, 3, 5. i ihpu input high current -10 0 +10 a v ih = v dd , notes 1, 3 i il input low current -10 0 +10 a v il = gnd, notes 2, 3 i ih input high current -10 0 +10 a v ih = v dd , notes 2, 3
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 410 symbol parameter min typ max units conditions c in input capacitance 5 pf all pins. excludes package. package typically 2 pf. note 5. c out output capacitance 5 pf all pins. excludes package. package typically 2 pf. note 5. c io bi-directional capacitance 5 pf all pins. excludes package. package typically 2 pf. note 5. l pin pin inductance 2 nh all pins. note 5. i ddop 3.3 operating current. 60 ma v dd3.3 = 3.6v, v dd2.5 = 2.7v, outputs unloaded. hsclk=77.76 mhz. sclk=gsclk[0]. i ddop 2.5 operating current. 395 ma v dd3.3 = 3.6v, v dd2.5 = 2.7v, outputs unloaded. hsclk=77.76 mhz. sclk=gsclk[0]. notes on d.c. characteristics: 1. input pin or bi-directional pin with internal pull-up resistor. 2. input pin or bi-directional pin without internal pull-up resistor. 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. input pin or bi-directional pin with internal pull-down resistor. 5. typical values are given as a design aid. the product is not tested to the typical values given in the data sheet.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 411 6. input pin is 5-volt tolerant.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 412 17 microprocessor interface timing characteristics (t a = -40c to +85c, v dd3.3 = 3.3 v 0.3 v, v dd2.5 = 2.5 v 0.2 v) table 9 - microprocessor interface read access symbol parameter min max units ts ar address to valid read set-up time 10 ns th ar address to valid read hold time 5 ns ts alr address to latch set-up time 10 ns th alr address to latch hold time 10 ns tv l valid latch pulse width 5 ns ts lr latch to read set-up 0 ns th lr latch to read hold 5 ns ts rwb rwb to read set-up 10 ns th rwb rwb to read hold 5 ns tp rd valid read to valid data propagation delay 70 ns tz rd valid read negated to output tri-state 20 ns tz inth valid read negated to output tri-state 50 ns
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 413 figure 30 - microprocessor interface read access timing (intel mode) (csb+rdb) intb tz inth valid data d[7:0] tp rd tz rd ts ar th ar valid address a[13:0] ale ts alr tv l ts lr th alr th lr
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 414 figure 31 - microprocessor interface read access timing (motorola mode) intb tz int (csb & e) valid data d[7:0] tp rd tz rd valid address a[13:0] ale ts alr tv l ts lr th alr th lr th ar rwb ts rwb th rwb ts ar
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 415 notes on microprocessor interface read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[7:0]). 3. in intel mode, a valid read cycle is defined as a logical or of the csb and the rdb signals. 4. in motorola mode, a valid read cycle is defined as a logical and of the e signal, the rwb signal and the inverted csb signal. 5. microprocessor interface timing applies to normal mode register accesses only. 6. in non-multiplexed address/data bus architectures, ale should be held high, parameters ts alr , th alr , tv l , and ts lr are not applicable. 7. parameter th ar and ts ar are not applicable if address latching is used. 8. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 9. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 416 table 10 - microprocessor interface write access symbol parameter min max units ts aw address to valid write set-up time 10 ns ts dw data to valid write set-up time 20 ns ts alw address to latch set-up time 10 ns th alw address to latch hold time 10 ns tv l valid latch pulse width 5 ns ts lw latch to write set-up 0 ns th lw latch to write hold 5 ns ts rwb rwb to write set-up 10 ns th rwb rwb to write hold 5 ns th dw data to valid write hold time 5 ns th aw address to valid write hold time 5 ns tv wr valid write pulse width 40 ns
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 417 figure 32 - microprocessor interface write access timing (intel mode) th dw valid data d[7:0] tv wr ts aw th aw ts dw (csb+wrb) a[13:0] valid address ale tv l ts alw ts lw th alw th lw
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 418 figure 33 - microprocessor interface write access timing (motorola mode) tv wr (csb & e) a[13:0] valid address th dw valid data d[7:0] ts dw ale tv l ts alw ts lw th alw th lw th aw ts aw rwb ts rw b th rwb notes on microprocessor interface write timing: 1. in intel mode, a valid write cycle is defined as a logical or of the csb and the wrb signals. 2. in motorola mode, a valid write cycle is defined as a logical and of the e signal, the inverted rwb signal and the inverted csb signal.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 419 3. microprocessor timing applies to normal mode register accesses only. 4. in non-multiplexed address/data bus architectures, ale should be held high, parameters ts alw , th alw , tv l , and ts lw are not applicable. 5. parameters th aw and ts aw are not applicable if address latching is used. 6. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 7. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 8. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 420 18 tupp+622 timing characteristics (t a = -40c to +85c, v dd3.3 = 3.3 v 0.3 v, v dd2.5 = 2.5 v 0.2 v) table 11 - tupp+622 input timing for sclk (figure 34) symbol description min max units sclk frequency (nominally 19.44 mhz ) 20 mhz sclk duty cycle 40 60 % ts id id[7:0], id[15:8], id[23:16], id[31:24] set-up time 3ns th id id[7:0], id[15:8], id[23:16], id[31:24] hold time 1.5 ns ts idp idp[4:1] set-up time 3 ns th idp idp[4:1] hold time 1.5 ns ts pl ipl[4:1] set-up time 3 ns th pl ipl[4:1] hold time 1.5 ns ts c1j1 ic1j1[4:1] set-up time 3 ns th c1j1 ic1j1[4:1] hold time 1.5 ns ts tmf itmf[4:1] and otmf[4:1] set-up time 3 ns th tmf itmf[4:1] and otmf[4:1] hold time 1.5 ns ts tpl itpl[4:1] set-up time 3 ns th tpl itpl[4:1] hold time 1.5 ns ts tv5 itv5[4:1] set-up time 3 ns th tv5 itv5[4:1] hold time 1.5 ns ts ais iais[4:1] set-up time 3 ns th ais iais[4:1] hold time 1.5 ns
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 421 table 12 - tupp+622 input timing hsclk (figure 34) symbol description min max units hsclk frequency (nominally 77.76 mhz) 80 mhz hsclk duty cycle 40 60 % ts id id[7:0] set-up time 2 ns th id id[7:0] hold time 0 ns ts idp idp[1] set-up time 2 ns th idp idp[1] hold time 0 ns ts pl ipl[1] set-up time 2 ns th pl ipl[1] hold time 0 ns ts c1j1 ic1j1[1] set-up time 2 ns th c1j1 ic1j1[1] hold time 0 ns ts fp gsclk_fp set-up time 2 ns th fp gsclk_fp hold time 0 ns ts tmf itmf[1] and otmf[1] set-up time 2 ns th tmf itmf[1] and otmf[1] hold time 0 ns ts tpl itpl[1] set-up time 2 ns th tpl itpl[1] hold time 0 ns ts tv5 itv5[1] set-up time 2 ns th tv5 itv5[1] hold time 0 ns ts ais iais[1] set-up time 2 ns th ais iais[1] hold time 0 ns
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 422 figure 34 - input timing ts id th id id[7:0] ts pl th pl ipl[4:1] sclk hsclk ts c1j1 th c1j1 ic1j1[4:1] ts tmf th tmf itmf[4:1] otmf[4:1] ts idp th idp idp[4:1] id[15:8] id[23:16] id[31:24] ts tpl th tpl itpl[4:1] ts tv5 th tv5 itv5[4:1] ts ais th ais iais[4:1] ts fp th fp gsclk_fp
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 423 notes on input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 424 table 13 - tupp+622 stream output symbol description min max units tp od sclk high to od[7:0] valid 3.5 20 ns tp odp sclk high to odp[4:1] valid 3.5 20 ns tp tpl sclk high to otpl[4:1] valid 3.5 20 ns tp tv5 sclk high to otv5[4:1] valid 3.5 20 ns tp tpoh sclk high to tpoh[4:1] valid 3.5 20 ns tp ais sclk high to ais[4:1] valid 3.5 20 ns tp idle sclk high to idle[4:1] valid 3.5 20 ns tp oc1 sclk high to oc1j1v1[4:1] valid 3.5 20 ns tp opl sclk high to opl[4:1] valid 3.5 20 ns tp cout sclk high to cout[4:1] valid 3.5 20 ns tp od hsclk high to od[7:0] valid 1 9 ns tp odp hsclk high to odp[1] valid 1 9 ns tp tpl hsclk high to otpl[1] valid 1 9 ns tp tv5 hsclk high to otv5[1] valid 1 9 ns tp tpoh hsclk high to tpoh[1] valid 1 9 ns tp ais hsclk high to ais[1] valid 1 9 ns tp idle hsclk high to idle[1] valid 1 9 ns tp oc1 hsclk high to oc1j1v1[1] valid 1 9 ns tp opl hsclk high to opl[1] valid 1 9 ns tp cout hsclk high to cout[1] valid 1 9 ns
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 425 figure 35- stream output timing tp od od[7:0] tp tpl otpl[4:1] sclk/ hsclk tp odp odp[4:1] tp tv5 otv5[4:1] tp a is ais[4:1] tp idle idle[4:1] tp oc1 oc1j1v1[4:1] tp opl opl[4:1] tp tpoh tpoh[4:1] od[15:8] od[23:16] od[31:24] tp cout cout[4:1]
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 426 table 14 - tupp+622 path overhead output (figure 36) symbol description min max units pohck duty cycle (pohck is nominally 9.72 mhz. pohck is a divide by two of the system clock, sclk.) 40 60 % tp poh pohck low to poh[12:1] valid -5 25 ns tp pohfp pohck low to pohfp[12:1] valid -5 25 ns tp pohen pohck low to pohen[12:1] valid -5 25 ns tp rad pohck low to rad[4:1] valid -5 25 ns
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 427 figure 36 - path overhead output timing tp poh poh[12:1] tp pohen pohen[12:1] pohck tp pohfp pohfp[12:1] tp rad rad[4:1]
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 428 table 15 - jtag port interface (figure 37) symbol description min max units tck frequency 4 mhz tck duty cycle 40 60 % ts tms tms set-up time to tck 50 ns th tms tms hold time to tck 50 ns ts tdi tdi set-up time to tck 50 ns th tdi tdi hold time to tck 50 ns tp tdo tck low to tdo valid 2 50 ns
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 429 figure 37 - jtag port interface timing ts tms th tms tms tck ts tdi th tdi tdi tp tdo tdo tck notes on output timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. output propagation delays are measured with a 50 pf load on the outputs except where indicated. for output propagation delays measured with respect to the hsclk, a 30 pf load on the outputs are used.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 430 3. output propagation delays of signal outputs that are specified in relation to a reference output are measured with a 50 pf load on both the signal output and the reference output except where indicated.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 431 19 ordering and thermal information table 16 - ordering information part no. description PM5363-BI 304 super ball grid array (sbga) table 17 - thermal information ? theta jc part no. ambient temperature theta jc PM5363-BI -40c to 85c 1 c/w table 18 - maximum junction temperature PM5363-BI maximum junction temperature for long term reliability 105 c
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 432 table 19 - thermal information ? theta ja vs. airflow forced air (linear feet per minute) theta ja @ specified power convection 100 200 300 400 500 dense board 21.9 19.2 17.4 16.3 15.8 15.6 jedec board 14.7 13.0 11.8 11.0 10.4 10.0 figure 38 - theta ja vs. airflow plot PM5363-BI theta ja vs. airflow 0 10 20 30 conv 100 200 300 400 500 airflow (linear feet per minute) theta ja (deg c/watt) dense board jedec board notes on theta ja vs. airflow: 1. dense board ? board with 3x3 array of the same device with spacing of 4mm between device. 6 layer board (3 signal layers, 3 power layers). chart represents device in the center of the array. chart represents values obtained through simulation.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 433 2. jedec board ? single component on a board. 4 layer board (2 signal layers, 2 power layers), metallization length x width = 94 mm x 94 mm. board dimension = 114mmx142mm. jedec measurement as per eia/gesd51-1.
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 434 20 mechanical information figure 39 - mechanical drawing 304 pin super ball grid array (sbga)
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces proprietary and confidential to pmc-sierra, inc., and for its customers? internal use 435 notes
tupp+622 pm5363 tupp+622 datasheet pmc-1981421 issue 4 sonet/sdh tributary unit payload processor for 622 mbit/s interfaces none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchanta bility, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in t his document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the inform ation, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-inf ringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. ? 2000 pmc-sierra, inc. pmc-1981421 (r4) ref pmc-1981103 (r4) issue date: july 2000 pmc-sierra, inc. 105 - 8555 baxter place burnaby, bc canada v5a 4v7 604 .415.6000 contacting pmc-sierra, inc. pmc-sierra, inc. 105-8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com application information: apps@pmc-sierra.com web site: http://www.pmc-sierra.com

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